Hi,
I have a question about DDR DPLL configuration in AM437x Linux SDK.
In Linux SDK version v07.01.00.00, multiplier and divider of DDR DPLL
for GP-EVM are setup as following:
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[CLKINP=24MHz]
M = 400
N = 23
M2 = 1
M4 = 1
(These value will make DDR CLK to be 400MHz and DLL CLK to be 800MHz)
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but in latest SDK version v02.00.01.07, it's setup as following:
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[CLKINP=24MHz]
M = 50
N = 2
M2 = 1
M4 = 2
(These value will make DDR CLK to be 400MHz and DLL CLK to be 400MHz)
************************************
Why "M", "N", "M4" value been changed in the latest SDK?
Are there any reason for these changes?
best regards,
g.f.