Hi,
I have one question regarding " HW leveling" of AM5728.
The below is a part of the GEL file ( AM572x_prcm_config.gel) of AM5728 from TI.
-----------
dpll_ddr_config(uint32_t DDR_FREQ)
{
if (532 == DDR_FREQ)
{
GEL_TextOut("\tDDR DPLL clock config for %dMHz is in progress...\n",,,,, DDR_FREQ);
if (CM_IDLEST_DPLL(CM_CLKMODE_DPLL_DDR)&0x1)
{
GEL_TextOut("\tDDR DPLL already locked, now unlocking....\n");
dpll_unlock_sequence(CM_CLKMODE_DPLL_DDR);
}
/* CM_CLKSEL_DPLL_DDR DPLL MULT */
CM_CLKSEL_DPLL(CM_CLKMODE_DPLL_DDR) = 0x10A04;
/* CM_DIV_M2_DPLL_DDR */
CM_DIV_M2_DPLL(CM_CLKMODE_DPLL_DDR) = 0x2;
/* CM_DIV_M3_DPLL_DDR */
CM_DIV_M3_DPLL(CM_CLKMODE_DPLL_DDR) = 0x1;
/* CM_DIV_H11_DPLL_DDR */
CM_DIV_H11_DPLL(CM_CLKMODE_DPLL_DDR) = 0x8;
dpll_lock_sequence(CM_CLKMODE_DPLL_DDR);
GEL_TextOut("\tDDR DPLL clock config for %dMHz is in DONE!\n",,,,, DDR_FREQ);
}
else if (400 == DDR_FREQ)
{
GEL_TextOut("\tDDR DPLL clock config for %dMHz is in progress...\n",,,,, DDR_FREQ);
if (CM_IDLEST_DPLL(CM_CLKMODE_DPLL_DDR)&0x1)
{
GEL_TextOut("\tDDR DPLL already locked, now unlocking....\n");
dpll_unlock_sequence(CM_CLKMODE_DPLL_DDR);
}
/* CM_CLKSEL_DPLL_DDR DPLL MULT */
CM_CLKSEL_DPLL(CM_CLKMODE_DPLL_DDR) = 0xC804; //((200 << 8) | (5-1));
/* CM_DIV_M2_DPLL_DDR */
CM_DIV_M2_DPLL(CM_CLKMODE_DPLL_DDR) = 0x2;
/* CM_DIV_M3_DPLL_DDR */
CM_DIV_M3_DPLL(CM_CLKMODE_DPLL_DDR) = 0x1;
/* CM_DIV_H11_DPLL_DDR */
CM_DIV_H11_DPLL(CM_CLKMODE_DPLL_DDR) = 0x4;
dpll_lock_sequence(CM_CLKMODE_DPLL_DDR);
GEL_TextOut("\tDDR DPLL clock config for %dMHz is in DONE!\n",,,,, DDR_FREQ);
}
else
{
GEL_TextOut("\tDDR DPLL frequency %dMHz not supported, nothing done.\n",,,,, DDR_FREQ);
}
}
------------
When my customer used 400MHz DDR3 with HW leveling, it did not work well. At that time, I was advised to change H11 divider value from 0x4 to 0x8 in 400MHz subroutine from Siva-san via local TI FAE. As a result, customer could use HW leveling with 400MHz DDR3.
So I would like to know the reason why H11 divider was needed to change the value from 0x4 to 0x8. H11 divider must be 0x8 always regardless DDR3 Frequency?
Could you ask this my question to Siva-san?
I appreciate your quick reply.
Best regards,
Michi
