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AM335x TLV320AIC3120 integration problems

Other Parts Discussed in Thread: TLV320AIC3120

Are there any examples (schematics and/or device tree snippets) of integrating an AM335x and a TLV320AIC3120 audio codec? I've spent a tremendous amount of time trying to get audio playback working and have not had success. Below are some segments of my device tree. The compatible... line was me following the example to modify the davinci-evm.c code within the kernel to add support.

The issue that I'm having is upon playback, I receive a "write error: Input/output error". Upon scoping the data lines, I see that MCLK is successfully generated by the AM335x for a very short period, then it stops being generated. I also see I2C communication to/from the '3120 during the same period. I feel that if MCLK continued to be generated, I'd successfully have audio.

This is using the linux-ti-staging-4.1 recipe from meta-ti (e.g. same kernel build as part of processor SDK).

&mcasp0 {
   pinctrl-names = "default";
   pinctrl-0 = <&mcasp0_pins>;
   status = "okay";
   op-mode = <0>; /* MCASP_IIS_MODE */
   tdm-slots = <2>;
   num-serializer = <16>;
   serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
      1 2 0 0
      0 0 0 0
      0 0 0 0
      0 0 0 0
   >;
   tx-num-evt = <1>;
   rx-num-evt = <1>;
};


sound {
   compatible = "ti,tlv320aic31xx-audio";
   ti,model = "AUDIO";
   ti,audio-codec = <&tlv320aic3120>;
   ti,mcasp-controller = <&mcasp0>;
   ti,codec-clock-rate = <24000000>;
   ti,audio-routing =
      "Speaker", "SPK";
};

 

Ignore the poor quality of the MCLK signal.  This is a result of my scope probe being filtered at ~20 MHz (and the signal is 24 MHz).

  • I will forward this to the software team.
  • Hi,

    Ryan Allgaier said:
    Are there any examples (schematics and/or device tree snippets) of integrating an AM335x and a TLV320AIC3120 audio codec?

    You can find an audio dac porting guide here: 
       http://processors.wiki.ti.com/index.php/Sitara_Linux_Audio_DAC_Example 

    Refer to this wiki for steps on how to set dts, alsa machine layer, etc.. 

    As for your dts, I see that you use  compatible = "ti,tlv320aic31xx-audio"; Did you add the 

    {

      .compatible = "ti,tlv320aic31xx-audio", 

      .data = &evm_dai_tlv320aic31xx, 

    }, 

    in davinci_evm_dt_ids[] in sound/soc/davinci/davinci-evm.c. This should bind the tlv320aic3120 driver to the dts parameters. 

    Also the audio routing seems a bit odd, can you try the default routing for am335x evm or am335x evmsk: 
       

    ti,audio-routing =
        "Headphone Jack", "HPLOUT",
        "Headphone Jack", "HPROUT",
        "LINE1L", "Line In",
        "LINE1R", "Line In"; 

    Best Regards, 
    Yordan

  • Yordan, thanks for the reply. I did follow the linked guide to add ti,tlv320aic31xx-audio to davinci-evm.c. The kernel successfully adds a playback device and I'm able to execute aplay sample.wav, with aplay successfully finding an audio device (even though no audio comes out).
  • Hi,

    Have you checked your amixer settings? Perhaps there is something not set on user level (from rootfs, alsa settings), like enabling link, volume levels, etc..

    Best Regards,
    Yordan
  • I did verify all settings with alsamixer. I've tried virtually every combination of settings, and I still do not get audio. I do get the short burst of MCLK being active, yet it does not stay active long enough to clock any meaningful audio content.

    During the design phase, it was assumed that MCLK can be generated by the McASP. However on many EVM schematics, I see an external clock source for MCLK. For instance, the BBB schematic uses a standalone external clock, and the AM437x GP EVM uses a general purpose CLKOUTx instead of McASP MCLK. It is not yet clear to me why these design decisions were made.  In our design, MCLK is expected to be generated by the McASP module.

  • I was able to inject an external clock source into the '3120's MCLK signal (disconnecting the McASP master clock). When I do so, audio playback occurs successfully.

    Is there any way to cause the McASP to reliably generate the master clock? As mentioned previously, the McASP does successfully generate MCLK for a short period, then ceases transmitting it.