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AM335x McSPI interface with EDMA to ADS131E04

Other Parts Discussed in Thread: ADS131E04, AM3354, SYSBIOS

Hi, colleagues. 

Here are some details about hardware and software:

I have got my own custom board with AM3354 module from axonim and ads131e04 on it.

They connected threw SPI0. Drdy goes to gpio.

To make it works together I decided to use sysbios. My IDE is CCS Version: 6.1.3.00033, debug probe is tixds100v2. 

I have managed to run simple spi with polling to configure read ADC registers, configure it and set to RDATAC mode.

I have managed to run edma example from mcspiFlash_edma.c. 

I have managed to run edma transaction from one buffer to another after gpio event. (i used button to activate gpio event on falling adge)

Now, I'am trying to run chained transaction example from TRM, to make spi work synchronously with drdy, but it does not work. 

I understand that it is hard to say what's wrong, so I'am going to start with paramset.

Please, somebody, check my paramset initialisation.

Paramset number1:

EDMA3CCPaRAMEntry paramSet;  //struct from starterware, so it should be OK
paramSet.srcAddr = (unsigned int) &dummy_buf[0];      // declaration is volatile unsigned char  dummy_buf[4]={0,0,0,0};
paramSet.destAddr = (unsigned int) (SOC_SPI_0_REGS+MCSPI_TX(1)); // defines from starterware.
paramSet.aCnt = 11; // 2bytes for each channel of ADC + 3 status bytes
paramSet.bCnt = 1;
paramSet.cCnt = 1; 
paramSet.srcBIdx = 0; 
paramSet.destBIdx = 0;
// A - sync Transfer Mode is set in OPT.
// srCIdx and destCIdx set to zero since A-SYNC Mode is used.
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
paramSet.linkAddr = 0xFFFF; // Linking transfers in EDMA3 are not used.
paramSet.bCntReload = 0;
paramSet.opt = 0x00000000;
// SAM and DAM fields both are set to 0
paramSet.opt |= ((19 << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);  //19 - tccnum of spi0_ch1_rx event
paramSet.opt |= EDMA3CC_OPT_ITCCHEN|EDMA3CC_OPT_TCCHEN;  //from TRM example 
//starterware func
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_GPIOEVT0, &paramSet);  // EDMA3_GPIOEVT0 defined as 22

Paramset number2:

paramSet.srcAddr = (unsigned int) (SOC_SPI_0_REGS+MCSPI_RX(1)); 
paramSet.destAddr = (unsigned int) &Buffer[0]; // declared like - unsigned char Buffer[64];
paramSet.aCnt = 11; // 
paramSet.bCnt = 1; // 
paramSet.cCnt = 1; // 
paramSet.srcBIdx = 0; // The srcBidx should not be incremented since it is a h/w register.
paramSet.destBIdx = 1; // The destBidx should be incremented for every byte.
// A sync Transfer Mode.
// srCIdx and destCIdx set to zero since ASYNC Mode is used.
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
// Linking transfers in EDMA3 are not used.
paramSet.linkAddr = 0xFFFF;
paramSet.bCntReload = 0;
paramSet.opt = 0x00000000;
// Set TCC field in OPT with the tccNum.
paramSet.opt |= ((19 << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
// EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.
paramSet.opt |= EDMA3CC_OPT_TCINTEN;
// Now write the PaRam Set to EDMA3.
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 19, &paramSet);

Best Regards, Roman

  • I will notify the RTOS team.
  • Hi, Biser.

    Maybe you have seen some drivers on linux that use dma with gpio events, some sort of codec with drdy maybe?

    Best Regards, Roman 

  • sorry, I'm not a software expert. The software team have been notified and they will respond directly here.
  • Hi, Biser.

    I have manage to deal with this problem.

    The correct params are as follows:

    void SPI_TX_EDMA_ParamsInit(void){
    	EDMA3CCPaRAMEntry paramSet;
    	paramSet.srcAddr = (unsigned int) &dummy_buf[0];  // srcAddr holds address of memory location buffer.
    	paramSet.destAddr = (unsigned int) (SOC_SPI_0_REGS+MCSPI_TX(SPI_CSn));  // destAddr holds address of McSPI_TX register.
    	paramSet.aCnt = 1; 	// aCnt holds the number of bytes in an array.
    	paramSet.bCnt = 11; // bCnt holds the number of such arrays to be transferred.
    	paramSet.cCnt = 1;   // cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred.
    	paramSet.srcBIdx = 1; 
    	paramSet.destBIdx = 0;
    	// srCIdx and destCIdx set to zero since A-SYNC Mode is used.
    	paramSet.srcCIdx = 0;
    	paramSet.destCIdx = 0;
    	paramSet.linkAddr = EDMA3CC_OPT(GPIO_DMA_EVENT); // Linking transfers in EDMA3 are not used.
    	paramSet.bCntReload = 0;
    	paramSet.opt = 0x00000000;
    	// SAM and DAM fields both are set to 0
    	
    	paramSet.opt |= ((MCSPI_RX_EVENT << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);	
    	paramSet.opt |= EDMA3CC_OPT_ITCCHEN|EDMA3CC_OPT_TCCHEN|EDMA3CC_OPT_ITCINTEN|(1UL<<2); //ab-sync
    	EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, GPIO_DMA_EVENT, &paramSet);
    }
    
    void SPI_RX_EDMA_ParamsInit(void){
    	EDMA3CCPaRAMEntry paramSet;
    	paramSet.srcAddr = (unsigned int) (SOC_SPI_0_REGS+MCSPI_RX(SPI_CSn));  // srcAddr holds address of SPI Rx FIFO.
    	paramSet.destAddr = (unsigned int) &Buffer[0]; 	// destAddr is address of memory location named buffer.
    	paramSet.aCnt = 1;  	// aCnt holds the number of bytes in an array.
    	paramSet.bCnt = 12; // bCnt holds the number of such arrays to be transferred.
    	paramSet.cCnt = 1;      // cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred.
    	paramSet.srcBIdx = 0;   // The srcBidx should not be incremented since it is a h/w register.
    	paramSet.destBIdx = 1;  // The destBidx should be incremented for every byte.
    	// A sync Transfer Mode.
    	// srCIdx and destCIdx set to zero since ASYNC Mode is used.
    	paramSet.srcCIdx = 0;
    	paramSet.destCIdx = 0;
    	// Linking transfers in EDMA3 are not used.
    	paramSet.linkAddr = (EDMA3CC_OPT(MCSPI_RX_EVENT));
    	paramSet.bCntReload = 0;
    	paramSet.opt = 0x00000000;
    	// Set TCC field in OPT with the tccNum.
    	paramSet.opt |= ((MCSPI_RX_EVENT << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
    	// EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.
    	paramSet.opt |= EDMA3CC_OPT_TCINTEN;//ab-sync
    	// Now write the PaRam Set to EDMA3.
    	EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, MCSPI_RX_EVENT, &paramSet);
    }
    

    In SPI I programmed wcnt counter to 11, AFL, AEL remains 0. 

    As you can see bcnt of second params set is 12. If I write 11, variable Buffer will contain correct data shifted for 1 byte in right direction, so I will not receive last byte of information.

    Extra byte in bcnt solves the problem of loosing data, but data in buffer still shifted in 1 byte. 

    So the question is - is it normal behaviour? What am I doing wrong? 

    If it is neccesary, I can provide you oscillograms and full initialisation code. 

  • Thanks for updating the thread with your results!
  • You are welcome!
    But I have got another problem.
    Data in my RX buffer did not change from transaction to transaction. (I mean from drdy event to drdy event).
    To solve the problem I have to reload params from ISR.
    Is it bug or I miss somethink?
    I'am still waiting your software team comment.

    Best regards, Roman