Hi,
I have some question regarding the implementation of IO Delay Recalibration sequence after AVS setting of VD_CORE.
I already got some advices form other post ( https://e2e.ti.com/support/arm/sitara_arm/f/791/t/523714 ). And I was advised the below points.
* The AVS voltages should only be set once per boot-up cycle.
* The basic configuration sequence is to set the AVS voltage and then perform the IO Delay Recalibration Sequence. This configuration would only have to happen once.
My customer uses AVS voltage in their system. But customer does not implement IO Dealy Recalibration Sequence yet. So customer is considering to do it.
Customer's system is the below.
XLoader - - - - - PAD configuration , clock setting, etc.
BOOT - - - - - I2C setting, AVS setting
If possible, customer does not want big change for loader and boot.
Questions are below.
1.From the description of IO Delay Recalibration sequence in TRM, I2C interface setting (for PMIC) is required prior to PAD configuration. In other words, AVS setting must be completed before the PAD cofiguration. Is my understanding right?
2. The below sequence is allowed?
1) I/O Delay Recalibration Sequence is executed (Including PAD configuration) in xloader.
2) AVS is set in BOOT.
3) After AVS completion, IO Delay Recalibration Sequence is executed again (except for Step6 (PAD configuration)).
I appreciate your quick reply.
Best regards,
Michi