AM571x EMIF_OCP_CONFIG register

Hi Kazu,

Here are some hints regarding EMIF priority:

The MA_PRIORITY[2:0] PRIORITY field is the MPU MA path equivalent of the DMM PEG priority for the rest of the system traffic to the EMIF.
The typical scenarios in which this register could have to be modified is

(1) The MPU does not seem to be able to complete its activities in the required time and a bandwidth/latency of access bottle neck is identified to the EMIF where other initiators seem to be getting higher priority while accessing EMIF vs MPU. In that case the PRIORITY may be increased to any number between 0x5 and 0x7 to ensure MPU gets a fair share of bandwidth and the rest of the system traffic is also okay.

(2) The MPU accesses to the EMIF need to be controlled with respect to another initiator (for eg. M4) to indicate that when ever an M4 transaction and MPU transaction both arrive at EMIF and we want the M4 transaction to be serviced before MPU, the MA_PRIORITY[2:0] PRIORITY can be configured to be lower than the M4 DMM PEG Priority for the EMIF to prioritize M4 vs MPU.

The EMIF additionally also provides a knob which allows controlling MPU traffic vs the rest of the system traffic in AM57x via the configuration of EMIF_OCP_CONFIG register. Based on the balance of the configuration in this register and the initiator based PRIORITY fields the EMIF internally decides which transactions to service first. Some details on the arbitration is given in 15.3.4.1.4 Arbitration of Commands in the Command FIFO of the AM57x TRM.

Regards,
Pavel