Hi Everyone,
Once I wake the system up from CORE off. DPLL4 remains in bypass stop mode.
Now after coming back from OFF I have tried to bring DPLL4 back to lock mode but it’s not working. It was not able to lock at the desired multiplier and divider value. However when I write some other value, let say 0x0 and then write the desired value in CM_CLKSEL2_PLL; It gets locked but serial driver is putting out garbage, which means that frequency being generated is not as programmed. Please note that the multiplier and divider values are correct verified using Linux and TI Clock Tree Tool.
CM_CLKSEL2_PLL = 0x0481b00c
I am also not sure about the AUTOIDLE bit against DPLL4 in CM_AUTOIDLE_PLL register. This bit is not having any effect on system. Do we need to enable this bit and also save it PRCM context save.
Also please note that I following the lock sequence. First I put the DPLL4 in bypass mode. Then after setting the desired multiplier and divider I wait for the DPLL4 to get locked. In my case if I do not write the CM_CLKSEL2_PLL register twice as mentioned above, DPLL4 never gets locked.
I can provide register dumps.
Thanks a lot for help,
Haider Miraj