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phy LAN8740 Dual mac ethernet problem (AM335X)

Other Parts Discussed in Thread: AM3352

Hi All,

        we are using lan8740 (two of them) in dual emac mode(RMII) for a custom board using AM3352 (based on am335x-evmsk). These lan8740 phys are connected to LAN9500 usb-ethernet phys on the custom board. After configuring the dts file we find the device getting registered from the below logs, But the ethernet link shows it is down. The LAN9500 is connected to PC on the USB side.

         --LAN8740--LAN9500--PC
AM3352->|
         --LAN8740--LAN9500--PC


libphy: Fixed MDIO Bus: probed
[    1.227588] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[    1.233735] davinci_mdio 4a101000.mdio: detected phy mask ffffffbe
[    1.241397] libphy: 4a101000.mdio: probed
[    1.245440] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8740--------->
[    1.254018] davinci_mdio 4a101000.mdio: phy[6]: device 4a101000.mdio:06, driver SMSC LAN8740--------->
[    1.263367] cpsw 4a100000.ethernet: Detected MACID = 68:9e:19:87:e8:ad
[    1.271077] cpsw 4a100000.ethernet: cpsw: Detected MACID = 68:9e:19:87:e8:af


net eth1: initializing cpsw version 1.12 (0)
net eth0: initialized cpsw ale version 1.4
net eth1: phy found : id is : 0x7c111
IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
net eth0: initializing cpsw version 1.12 (0)
net eth0: phy found : id is : 0x7c111
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

It seems that the auto negotiation is failing. But the root cause for this is not clear
As per the data sheet of LAN8740 it says a hardware reset is required. "A hardware reset (nRST assertion) is required following power-up." But we dont find any code/patch for linux kernel implementing such a hardware reset.

There is a provision in dt file to set the "reset-gpios" and "reset-delay-us" in the MDIO Controller Device Tree Bindings
 - reset-gpios       : array of GPIO specifier for PHY hardware reset control
 - reset-delay-us    : reset assertion time [in microseconds]

We are exploring the possibility of using the above dt options to implement hardware reset. But we have our doubts since we did not find any such implementation for lan8740. The custom board has a onboard switch to hardware reset the lan8740. We tried hardware reset after uboot and before kernel boot using the switch but still the auto negotiation failed for lan8740.

Our questions are
1) Is hardware reset after power-on mandatory for lan8740?
   If yes what is the best method to deliver this hardware reset (through above mentioned dt configurations) ?
2) Is there any method to test the lan8740 (Ex: HW loopback, etc).

Below we have the Device Tree (am335x-evmsk.dts) with all configuration of Ethernet PHY (Kindly suggest if any changes needs to be done)
       
        cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                        /* Slave 1 */

                        0x144 ( PIN_INPUT_PULLDOWN | MUX_MODE0 )  /* (H18) rmii1_refclk.rmii1_refclk */
                        0x10c ( PIN_INPUT_PULLDOWN | MUX_MODE1 )  /* (H17) mii1_crs.rmii1_crs_dv */
                        0x110 ( PIN_INPUT_PULLDOWN | MUX_MODE1 )  /* (J15) mii1_rxer.rmii1_rxer */
                        0x114 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (J16) mii1_txen.rmii1_txen */
                        0x128 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (K17) mii1_txd0.rmii1_txd0 */
                        0x124 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (K16) mii1_txd1.rmii1_txd1 */
                        0x140 ( PIN_INPUT_PULLDOWN | MUX_MODE1 )  /* (M16) mii1_rxd0.rmii1_rxd0 */
                        0x13c ( PIN_INPUT_PULLDOWN | MUX_MODE1 )  /* (L15) mii1_rxd1.rmii1_rxd1 */

                        0x98 ( PIN_INPUT_PULLDOWN | MUX_MODE7 )   /* (U6) gpmc_wen.gpio2_4  fs-lan8740int */

                        /*Slave 2*/

                        0x70 ( PIN_INPUT_PULLDOWN | MUX_MODE3 )   /* (T17) gpmc_wait0.rmii2_crs_dv */
                        0x74 ( PIN_INPUT_PULLDOWN | MUX_MODE3 )   /* (U17) gpmc_wpn.rmii2_rxer */
                        0x40 ( PIN_OUTPUT_PULLDOWN | MUX_MODE3 )  /* (R13) gpmc_a0.rmii2_txen */
                        0x54 ( PIN_OUTPUT_PULLDOWN | MUX_MODE3 )  /* (V15) gpmc_a5.rmii2_txd0 */
                        0x50 ( PIN_OUTPUT_PULLDOWN | MUX_MODE3 )  /* (R14) gpmc_a4.rmii2_txd1 */
                        0x6c ( PIN_INPUT_PULLDOWN | MUX_MODE3 )   /* (V17) gpmc_a11.rmii2_rxd0 */
                        0x68 ( PIN_INPUT_PULLDOWN | MUX_MODE3 )   /* (T16) gpmc_a10.rmii2_rxd1 */
                        0x108 ( PIN_INPUT_PULLDOWN| MUX_MODE1 )   /* (H16) gmii1_col.rmii2_refclk */
                        0x14 ( PIN_INPUT_PULLDOWN | MUX_MODE7 )   /* (V8) gpmc_ad5.gpio1_5 fs-lan8740 int*/
                >;
        };

cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                        /* Slave 1 reset value */
                        0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii1_int */
                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_crs_dv */
                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rxer */
                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_txen */
                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_td1 */
                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_td0 */
                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rd1 */
                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rd0 */
                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_refclk */

                        /* Slave 2 reset value*/
                        0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_txen */
                        0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_td1 */
                        0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_td0 */
                        0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rd1 */
                        0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rd0 */
                        0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_crs_dv */
                        0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rxer */
                        0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_int */
                        0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii2_refclk */
                >;
        };

        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
                >;
        };

        davinci_mdio_sleep: davinci_mdio_sleep {
           pinctrl-single,pins = <
                        /* MDIO reset value */
                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
        };

&mac {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
        dual_emac = <1>;
        status = "okay";
};

&davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
        status = "okay";
};

&cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
        phy-mode = "rmii";
        dual_emac_res_vlan = <2>;
};

&cpsw_emac1 {
        phy_id = <&davinci_mdio>, <6>;
        phy-mode = "rmii";
        dual_emac_res_vlan = <3>;
};

&phy_sel {
        rmii-clock-ext;

  • Hi Santosh,

    How did you strap the PHY's MODE[2:0] pins on the PCB? Assuming that you strapped them correctly for Auto-Negotiation Enabled (Section 3.7.2 of the Microchip data manual) on your PCB, it's possible/probable that the correct strapping isn't being latched in the absence of a valid nRST after power-up. This can be verified by reading the PHY's AUTO_NEGOTIATION_ADVERTISEMENT registers at PHY index d04.

    Check these and let us know what you find.

  • Hi DK, Sorry for the late response. I have enabled certain dbeug msgs and taken the logs. I have marked for the values which u have asked.

    dmesg.txt|218 col 38| [    1.241420] SMSC LAN8740 4a101000.mdio:06: phy_probe 1372                                                             
    dmesg.txt|221 col 68| [    1.254046] davinci_mdio 4a101000.mdio: phy[6]: device 4a101000.mdio:06, driver SMSC LAN8740
    dmesg.txt|385 col 38| [   16.237982] SMSC LAN8740 4a101000.mdio:06: phy_connect 522
    dmesg.txt|386 col 38| [   16.237999] SMSC LAN8740 4a101000.mdio:06: phy_connect_direct 475
    dmesg.txt|387 col 38| [   16.238013] SMSC LAN8740 4a101000.mdio:06: phy_attach_direct 638
    dmesg.txt|388 col 38| [   16.238027] SMSC LAN8740 4a101000.mdio:06: phy_init_hw 596
    dmesg.txt|389 col 38| [   16.238565] SMSC LAN8740 4a101000.mdio:06: phy_resume 803
    dmesg.txt|390 col 38| [   16.238578] SMSC LAN8740 4a101000.mdio:06: genphy_resume 1286
    dmesg.txt|391 col 38| [   16.238823] SMSC LAN8740 4a101000.mdio:06: phy_prepare_link 458
    dmesg.txt|393 col 38| [   16.317522] SMSC LAN8740 4a101000.mdio:06: +++++++phy_start 789
    dmesg.txt|394 col 38| [   16.317555] SMSC LAN8740 4a101000.mdio:06: phy_start 798 PHY_READY:
    dmesg.txt|411 col 38| [   17.238542] SMSC LAN8740 4a101000.mdio:06: +++++++phy_state_machine 838
    dmesg.txt|412 col 38| [   17.238578] SMSC LAN8740 4a101000.mdio:06:  phy_state_machine 853 PHY_UP:
    dmesg.txt|413 col 38| [   17.238592] SMSC LAN8740 4a101000.mdio:06: +++++++phy_start_aneg 493
    dmesg.txt|414 col 38| [   17.238605] SMSC LAN8740 4a101000.mdio:06: genphy_config_aneg 951
    dmesg.txt|415 col 38| [   17.238616] SMSC LAN8740 4a101000.mdio:06: genphy_config_advert 833
    dmesg.txt|416 col 38| [   17.238627] SMSC LAN8740 4a101000.mdio:06: santosh in genphy_config_advert in phy_device
    dmesg.txt|417 col 38| [   17.238718] SMSC LAN8740 4a101000.mdio:06:  genphy_config_advert read 1a1-------------------------------->
    dmesg.txt|418 col 38| [   17.238732] SMSC LAN8740 4a101000.mdio:06:  genphy_config_advert before write de1---------------------->
    dmesg.txt|419 col 38| [   17.238848] SMSC LAN8740 4a101000.mdio:06:  genphy_config_advert after write de1 0----------------------->
    dmesg.txt|420 col 38| [   17.239108] SMSC LAN8740 4a101000.mdio:06: genphy_restart_aneg 926
    dmesg.txt|421 col 38| [   17.239238] SMSC LAN8740 4a101000.mdio:06: genphy_config_aneg 978i result = 0
    dmesg.txt|423 col 38| [   17.239258] SMSC LAN8740 4a101000.mdio:06: PHY state change UP -> AN
    dmesg.txt|438 col 38| [   18.237793] SMSC LAN8740 4a101000.mdio:06: +++++++phy_state_machine 838
    dmesg.txt|439 col 38| [   18.237829] SMSC LAN8740 4a101000.mdio:06:  phy_state_machine 858 PHY_AN:
    dmesg.txt|440 col 38| [   18.237843] SMSC LAN8740 4a101000.mdio:06: genphy_read_status 1059
    dmesg.txt|441 col 38| [   18.237855] SMSC LAN8740 4a101000.mdio:06: genphy_update_link 1018
    dmesg.txt|443 col 38| [   18.258637] SMSC LAN8740 4a101000.mdio:06: PHY state change AN -> NOLINK
    dmesg.txt|448 col 38| [   19.257897] SMSC LAN8740 4a101000.mdio:06: +++++++phy_state_machine 838
    dmesg.txt|449 col 38| [   19.257932] SMSC LAN8740 4a101000.mdio:06:  phy_state_machine 890 PHY_NOLINK:
    dmesg.txt|450 col 38| [   19.257947] SMSC LAN8740 4a101000.mdio:06: genphy_read_status 1059
    dmesg.txt|451 col 38| [   19.257959] SMSC LAN8740 4a101000.mdio:06: genphy_update_link 1018
    dmesg.txt|452 col 38| [   19.278129] SMSC LAN8740 4a101000.mdio:06:  phy_state_machine 895 err = 0:
    dmesg.txt|454 col 38| [   19.278171] SMSC LAN8740 4a101000.mdio:06: PHY state change NOLINK -> NOLINK
    dmesg.txt|457 col 38| [   20.277880] SMSC LAN8740 4a101000.mdio:06: +++++++phy_state_machine 838
    dmesg.txt|458 col 38| [   20.277916] SMSC LAN8740 4a101000.mdio:06:  phy_state_machine 890 PHY_NOLINK:

    Thanks in advance