Our customer wants to reconfigure GPMC in an interval between accesses. How can this be implemented?
Section 7.1.2.3.8.1 on TRM (SPRUH73N) describes:
"Chip-select configuration (base and mask address or any protocol and timing settings) must be performed
while the associated chip-select is disabled through the GPMC_CONFIG7_i[6] CSVALID bit. In addition, a
chip-select configuration can only be disabled if there is no ongoing access to that chip-select. This
requires activity monitoring of the prefetch or write-posting engine if the engine is active on the chip-select.
Also, the write buffer state must be monitored to wait for any posted write completion to the chip-select."
It requires to monitor the write buffer state, the prefetch or write-posting engine activity state. Which are fields in the registers indicating each state?
Best regards,
Daisuke