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operating TSC_ADC clock of specification of AM3352 ?

shigehiro tsuda
Mastermind 9490 points
Other Parts Discussed in Thread: AM3352

Hi,

The problem that there is not is up to 0 with being working, and FSM_BUSY of the ADCSTAT register of the AD conversion becoming 1 when our customer operate the frequency of the TSC_ADC conversion as 3MHz.
When AD conversion fell into an error state, what will the procedure of the return method have?

In Table 12-2 TSC_ADC Clock Signals of TRM of AM335x, ADC_CLK becomes MAX24MHz, but ADC_CLK sets it to 3MHz with the data sheet of AM3352, and it is recommended that sampling rate uses it in typ 200kSPS.
Even if ADC_CLK uses MAX24MHz, will the operation be guaranteed?

AD converts six analog values and is going to store it in FIFO0 and makes a value of STEPCONFIG register Mode Field from step1 to step6 00(one-shot).
Data after six AD conversion should be in FIFO0 when I make each step enable then, but the following difference occurs.
Data after seven conversion may be in FIFO0 when our customer make operating frequency of the AD conversion 3Mhz.
Data after six conversion are in FIFO0 by all means when I make operating frequency of the AD conversion 24Mhz.

Two times of AD conversion seems to be done in spite of one-shot mode one analog value.
Will there be this solution?

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru 55295 points

    The frequency reference in Table 12-2 is describing the clock being sourced to the ADC.  The ADC has a clock pre-divider that must be used to reduce the operating frequency to less than or equal to 3MHz.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 9490 points
    Hi Paul,
    Thank you for quick reply.
    I understand that ADC CLK must be used the operating frequency to less than or equal to 3MHz.

    I would like the answer to other questions.

    1.
    The problem that there is not is up to 0 with being working, and FSM_BUSY of the ADCSTAT register of the AD conversion becoming 1 when our customer operate the frequency of the TSC_ADC conversion as 3MHz.
    When AD conversion fell into an error state, what will the procedure of the return method have?

    2.
    AD converts six analog values and is going to store it in FIFO0 and makes a value of STEPCONFIG register Mode Field from step1 to step6 00(one-shot).
    Data after six AD conversion should be in FIFO0 when I make each step enable then, but the following difference occurs.
    Data after seven conversion may be in FIFO0 when our customer make operating frequency of the AD conversion 3Mhz.
    Data after six conversion are in FIFO0 by all means when I make operating frequency of the AD conversion 24Mhz.

    Two times of AD conversion seems to be done in spite of one-shot mode one analog value.
    Will there be this solution?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to peaves
    Mastermind 9490 points
    Hi Paul,

    About this problem, is there any update information?
    The clock of the ADC should not be less than 3MHz, but 4MHz or more seem to be good.
    It occurs by the following setting of the STEPCONFIGX register.
    averaging[2..4]: 000 = No average.
    Mode[0..1]:00 = SW enabled, one-shot.

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru 55295 points
    I don't understand the issue. You may need to provide a better explanation of the problem.

    It sounds like you may have some software configuration issue. Can you provide information on the software being used?

    Regards,
    Paul
  • 0 in reply to peaves
    Intellectual 510 points
    TRM Table 12-2 note 1 states that pre-divider is only required to be set if master clock is above 24MHz. With a clock of 26MHz for example the clock needs to be divided by 2, resulting in a 13MHz max ADC clock which is below the achievable maximum of 24MHz.
    So from TRM point of view I would assume ADC clock can be up to 24MHz (which also works on BBB). The data sheet also does not limit ADC clock to 3MHz in my opinion. It just specifies the ADC performance for y (typical) clock of 3MHz.
    Is there any statement that really limits ADC clock to 3MHz?
    However continuous sampling at 24MHz may cause problems with throughput from ADC to memory (but I did not test this).
  • 0 in reply to Thomas Langhammer
    TI__Guru 55295 points
    The divided clock that runs the ADC must not be greater than 3MHz.

    The TRM reference of 24MHz is the maximum pre-divided clock frequency that will yield the maximum divided ADC clock frequency of 3MHz. If using a 26MHz pre-divided clock you must divide it by 9 to stay less than or equal to 3MHz, which gives a divided clock frequency of 2.89MHz. If using a 25MHz pre-divided clock you must divide it by 9 to stay less than or equal to 3MHz, which gives a divided clock frequency of 2.78MHz. If using a 19.2MHz pre-divided clock you must divide it by 7 to stay less than or equal to 3MHz, which gives a divided clock frequency of 2.749MHz. However, if using a 24MHz pre-divided clock you must divide it by 8 to stay less than or equal to 3MHz, which gives a divided clock frequency of 3.00MHz.

    Regards,
    Paul