I have a custom design with AM3352 and DDR3 design based on beaglebone black. However this design needs to work at high ambient temperatures, so I changed the refresh period from 7.8µs (setting of BBB) to 3,9µs according to the requirements mentioned in the DDR3 data sheet.
My concern is about the setting of the ZQ_CONFIG register (offset 0xC8 in EMIF4D register space). TRM section 7.3.5.29 describes bits 15-0 as reg_zq_interval, which is interpreted as a number of refresh intervals. I did not find any further description, but I can see that all DDR3 reference designs set bits15..0 to the value 0x4BE4, but they also set the refresh rate always to 7,8µs.
Do I need to adjust reg_zq_interval when I change the refresh interval, in order to result in the same (absolute) time for ZQCS calibration, or shall the reg_zq_interval value stay the same, resulting in the same cycle ratio of refresh/ZQCS but a higher (absolute) ZQCS calib rate?
