AM5718: PCIe with Pericom switch unstable GEN2 connection

Robert Finger

Part Number: AM5718
Other Parts Discussed in Thread: AM5728

Team,

On an AM5718 customer design there is Pericom PI7C9X2G404SL PCIe bridge. But in Linux the bridge is not always detected. If we limit PCIe to GEN1, the bridge is always detected and operates stable.

Attached log files for the working and one for the non-working case (both using GEN2).
lspci -xxxx working.txt

lspci -xxxx NOT working.txt

root@beaglebone:~#
root@beaglebone:~# lspci
0000:00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01)
0000:01:00.0 Bridge: xxx xxxxx xxxxxx Multifunction IP core
0001:00:00.0 Non-VGA unclassified device: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01)
root@beaglebone:~# lspci -xxxx
0000:00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01)
00: 4c 10 88 88 47 05 10 00 01 00 04 06 10 00 01 00
10: 00 00 10 20 00 00 02 20 00 01 01 00 f0 00 00 00
20: 00 22 f0 2f f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 01 00
40: 01 50 03 5a 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 81 00 00 c0 48 9b 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 00 42 00 01 80 00 00 1f 28 00 00 22 3c 73 00
80: 48 00 11 70 00 00 00 00 c0 03 40 00 08 00 00 00
90: 00 00 00 00 1f 04 00 00 00 00 00 00 06 00 00 00
a0: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
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4b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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5a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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6a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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9a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

0000:01:00.0 Bridge: xxx xxxxx xxxxxx Multifunction IP core
00: 88 1a 45 4d 40 01 10 00 00 00 80 06 10 00 00 00
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0001:00:00.0 Non-VGA unclassified device: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01)
00: 4c 10 88 88 40 01 10 00 01 00 00 00 10 00 01 00
10: 08 00 00 00 08 00 00 00 00 01 01 00 00 00 00 00
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3f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
400: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
410: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
420: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
430: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
440: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
450: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
460: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
470: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
480: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
490: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
4f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
500: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
510: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
530: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
540: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
550: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
560: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
570: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
580: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
590: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
5f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
600: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
610: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
620: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
630: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
640: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
650: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
660: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
670: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
680: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
690: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
6f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
700: 40 00 c0 00 ff ff ff ff 04 00 00 07 00 0f 0f 1b
710: 20 01 03 00 00 00 00 00 00 40 00 00 80 02 00 00
720: 00 00 00 00 01 00 00 00 00 ee 52 00 00 00 20 08
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810: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
820: 00 60 45 9b 00 00 00 00 00 00 00 00 00 00 00 00
830: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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910: 00 00 00 00 ff 0f 00 00 00 00 00 00 00 00 00 00
920: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
930: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
940: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
950: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
960: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
970: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
990: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
9f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
aa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ab0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ac0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ad0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ae0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
af0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b40: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ba0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
be0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
bf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ca0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ce0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
cf0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
da0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
db0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
de0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
df0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ea0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
eb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ec0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ed0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ee0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ef0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fa0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fb0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fd0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

root@beaglebone:~#

There was already a discussion for the same topic in the following thread. It was about forcing PCIe to GEN1 as workaround:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/566421/2078367

Are there any PCIe registers that can be checked for further debugging?

Thanks,
Robert

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi Robert,

The PCIe experts have been notified. They will respond here.

0 user4759774 over 7 years ago

Intellectual 745 points

Hi Robert,

When I've sent patches, which forces GEN1 on PCIe to Linux mailing list, I've discover that there is another idea of how to do it in Linux community.

Some people from TI had different idea of how things should be done:

http://patchwork.ozlabs.org/patch/715437/

In our case we do want GEN1 operation from very beginning. Otherwise we encounter hangs.

Best regards,

Łukasz

0 lding over 7 years ago in reply to user4759774

TI__Guru* 95265 points

Lukasz, Robert,

patchwork.ozlabs.org/.../: Kishon is in our Linux development, I am in bare metal Processor SDK RTOS team. There are two approaches discussed to force GEN1: one is Target Link Speed" to Gen1 before setting LTSSM_EN, the other is clear CFG_DIRECTED_SPEED_CHANGE bit. Both works, the latter is more versatile. As you are using Linux, so the code or patch would come from Kishon. Please follow up with him with the desired method to force GEN1.

Back to the original question, why GEN2 is unstable in this AM5718 -----Pericom PI7C9X2G404SL PCIe bridge?

Only thing I knew is this errata for AM57x: www.ti.com/.../sprz429j.pdf

i925: PCI-Express Gen2 (5.0 GT/s) Operation Not Supported When Operating Junction
Temperature <0°C

If your opeartion is normal room temprature, I don't think this apply. We have tested several generic PCIE to NIC or PCIE to SATA cards connected to our AM57x EVM (PCIE RC) in GEN2 speed, we don't see any instablity issue.

From www.pericom.com/.../PI7C9X2G404SL, this switch also support GEN2. So I think the issue may come from the PCIE signal integrity. Do you have any measurement for that?

"PCIe registers that can be checked for further debugging" =====>On PCIE, you can continously monitor 0x51802104 bit 2:7 LTSSM_STATE field transition once the LTSSM_EN bit is set. You need to modify Linux kernel for this, and the state transition may show the failure/recovery sequence but not the cause.

There may be some PCIE PHY registers to initiate the bit error rate test, but I am not familiar with that and there is no SW examples how to configure and run it. Let me check with our HW team.

Regards, Eric

0 Tom Johnson 16214 over 7 years ago in reply to lding

TI__Mastermind 46460 points

Is this x1 or x2 PCIe link configuration? I am assuming that the Pericom switch is the Root Complex and the AM5718 is the End Point. Is this correct?

0 Robert Finger over 7 years ago in reply to Tom Johnson 16214

TI__Genius 16212 points

Eric, Tom,
Tests are done at room temperature.

It's a x1 configuration, PCIe subsystem 2 is used (PCIe SS 1 is connected to a FGPA). And AM57x is RC.

Thanks,
Robert

0 Tom Johnson 16214 over 7 years ago in reply to Robert Finger

TI__Mastermind 46460 points

Robert,

This is not clear to me. It appears that both PCIe ports are being used, each in an x1 configuration. SS1 to FPGA and SS2 to Pericom SW. Please clarify whether each is RC or EP. Also, please provide reference clock source for each. Are they both only working at the GEN1 rate?

Tom

0 user4759774 over 7 years ago in reply to Tom Johnson 16214

Intellectual 745 points

Dear All,

Test are done with AM5728 (AM5718 requires extra mapping of USB3.0 phy).

PCIe1 -> RC, GEN2 (FPGA) - it is always found

PCIe2 -> RC, GEN1 (Pericom) (GEN1 works)

Reference clock is generated from AM5728 (100MHz). Then it is "splitted"/buffered by other IC and provided to all PCIe/PCI devices.

Regarding Eric's question - I've checked LTSSM states:
- When Pericom works - I do see 0x11 - L0 state ( PCIECTRL_TI_CONF_DEVICE_CMD 0x5180 2104) after successful GEN2 configuration (without forcing to GEN1)

- When we have malfunction - the read LTSSM state is 0x00 - Detect.quiet.

Best regards,
Łukasz

0 lding over 7 years ago in reply to user4759774

TI__Guru* 95265 points

Lukasz,

For monitoring the ltssm state, I meant you could see something like: 0x00, 0x01, 0x6, 0x1, 0x2, 0x4, 0x11 .... that requires the SW to record every state transition very fast (use command like devmem2 to dump it is not fast enough), you may see it enters L0 then drop out. The SW monitoring only capture the transition, not the root cause of the failure. You still need some HW signal integrity test to find out.

Regards, Eric

0 -DK- over 7 years ago in reply to lding

TI__Mastermind 27720 points

In cases where two PCIe Gen2-capable link partners are unable to establish (or maintain) a Gen2 connection, the signal integrity of the interface should be examined first. Please refer to the Texas Instruments High Speed Layout Guidelines (www.ti.com/lit/pdf/spraar7) and ensure that the PCB layout meets the requirements for this device.

0 Robert Finger over 7 years ago in reply to -DK-

TI__Genius 16212 points

Hi,

Is there any detailed description about the SATA PHY registers? There is a note about recommended settings in the TRM, but no further details (Table 26-9 in AM571x and AM572x TRM). The AM57x PDK SW also sets these registers.

But when doing a register dump in Linux (after PCIe driver has loaded), the registers don't match the recommended values. Values are the same for working and non-working GEN2 (only registers mentioned in TRM shown):

xxx_xxx#0>mdahb 0x4A096000 33
AHB/AXI 00_4a096000 : 00000000
...
AHB/AXI 00_4a09600c : 00000000
...
AHB/AXI 00_4a09601c : 00000000
...
AHB/AXI 00_4a096028 : 02e33000
...
AHB/AXI 00_4a096038 : 00000000
...
AHB/AXI 00_4a096044 : 00000200
...

Might this cause the issue?

Thanks,
Robert

0 lding over 7 years ago in reply to Robert Finger

TI__Guru* 95265 points

Robert,

Our SW doesn't touch those registers, here is how they looks like in my system by default:

So the same as in your system. All the discription is in the TRM. Please try the suggestion from Dave and Tom, to check the PCIE signal integrity first.

Regards, Eric

0 Daniel Sommerfeldt over 7 years ago in reply to lding

Prodigy 245 points

Hi,

I have measured the PCIe eye diagram near the CPU pins (distance around 5mm) and at the load (Pericom switch), distance about 3inch.

Bitrate shows that this measured signal was GEN1.

The 100MHz clock is generated by the CPU!

PCIe Eye.zip

0 -DK- over 7 years ago in reply to Daniel Sommerfeldt

TI__Mastermind 27720 points

Did you include test points on the PCIe traces? I infer that from your post, but wanted to make sure.

0 Daniel Sommerfeldt over 7 years ago in reply to -DK-

Prodigy 245 points

No, there are no test points included. The trace from the CPU is connected to a configuration resistor, because the PCIe from the AM5718 and AM5728 are located on different pins. With the configuration resistor I can either connect the lane from the AM5718 or AM5728 to the module connector.

0 user4759774 over 7 years ago in reply to Daniel Sommerfeldt

Intellectual 745 points

Hi,

If I might ask (sorry to ask I'm not so experienced with high signals analyze) - why do we have such attenuation?

Is this something that can be fixed by DPLL PCIe configuration?

Best regards,
Łukasz

0 -DK- over 7 years ago in reply to user4759774

TI__Mastermind 27720 points

Your attenuation problem may be caused by reflections introduced by the option resistors in your design, but a cursory review of the data provided reveals several issues that could contribute to your inability to link train at Gen2:
- There is some pretty significant signal jitter which is usually a result of insufficient signal spacing (SPRAAR7, Section 3.1)
- Symmetry isn't maintained in the diff pairs (SPRAAR7, Section 3.3)
- Vias are not permitted on PCIe (SPRAAR7, Table 4)
- Signal bending rules don't appear to have been followed (SPRAAR7, Section 3.11)
- TI recommends that high-speed signal muxing through the use of option resistors be avoided, but when absolutely necessary, SMD discontinuity mitigation techniques should be implemented (SPRAAR7, Section 3.10).
- It appears that one of the PCIe signals crosses under the other (at the location of the option resistor). You may have an isolation layer present that just isn't being shown in the image, but I wanted to point it out just in case.

My recommendation is that you perform a top-down review of the PCB itself using SPRAAR7 as a guide. In parallel it might be useful to perform a simulation of your existing PCB design to better understand if Gen2 is at all possible.

0 -DK- over 7 years ago in reply to -DK-

TI__Mastermind 27720 points

Another note: you may want to try changing the equalization settings in the PHY to reduce the signal amplitude. This may/may-not be possible depending on how it is currently configured. The TRM has details on this functionality.

I need to correct myself ...manual amplitude adjustment is not available for PCIe.

0 Christopher Peters over 7 years ago in reply to -DK-

Genius 3370 points

We are also having an issue getting reliably to GEN2 with a 5728 connected to an Altera FPGA. GEN1 works every time, but GEN2 appears to fail the switch to 5G ending in Detect Quiet state and sometimes in Pre Detect Quiet. We connected a Lecroy Protocol Analyzer and we see sometimes the 5728 does the Link Down after getting L0 state at 2.5G, but never sends the Link Up at 5G. The FPGA sends Link Down at 2.5G then Link Up at 5G as expected. We are working on capturing the eye diagram. Mainly I posted this to get involved in this conversation.

0 user4759774 over 7 years ago in reply to Christopher Peters

Intellectual 745 points

Hi DK,

Just out of curiosity (and a bit off topic if I might):

I've read through the SPRAAR7 manual and there was no information about the DDR3 clock layout.

I suppose that there is another document describing guidelines for it (I've only found sprac36.pdf) ?
I'm most interested in serial clock layout (and its length, termination) recommendations - we do experience some "bit flip patterns" on MSB memory byte from the farthest memory.

Best regards,
Łukasz

0 -DK- over 7 years ago in reply to user4759774

TI__Mastermind 27720 points

Yes. Please refer to SPRABI1B. It's in the Technical Docs folder of the device landing page.

0 Tom Johnson 16214 over 7 years ago in reply to -DK-

TI__Mastermind 46460 points

Specific routing requirements for the DDR3 implemented on the AM5718 are contained in the Data Manual SPRS957 in section 8.2.

Tom

0 AC over 7 years ago in reply to Daniel Sommerfeldt

Intellectual 520 points

Hi,

I'm trying to test PCIe eye diagram.
Would you please share how to generate the test pattern and the test procedure on AM57xx?
And are you using Linux SDK?

Thank you very much.
AC

0 Christopher Peters over 7 years ago in reply to AC

Genius 3370 points

We were able to capture the eye diagram but we did not use any special test pattern or procedure. We did get a very expensive 33 GHz scope loaned to us with solder down probes. Since we were able to get the link into Gen2 sometimes, we kept initializing the link until we got Gen2 then collected the eye diagram. This exercise showed us the VOD from the FPGA to the AM5728 was low causing mask violations in the middle of the eye. We were able to increase the VOD and fix the mask violations. The eye from the 5728 to the FPGA looked ok, it could be better, but ok. I also noted on another thread that we discovered the Reset sequence for the PCIe susbsystem was not well documented in the TRM. Fixing that issue has allowed us to be able detect that Gen2 failed to initialize and reset and retry. Usually after no more than 4 retries, the link comes up and is stable. That thread is here: https://e2e.ti.com/support/arm/sitara_arm/f/791/t/574129

Here are the eye diagrams we collected.

5728 to FPGA

FPGA to 5728

Processors

Processors forum

AM5718: PCIe with Pericom switch unstable GEN2 connection