• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 2 answers
  • Subscribers 100 subscribers
  • Views 1791 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linux/AM3352: McSPI CS issue in U-boot

yimin bai1
Expert 1495 points
Part Number: AM3352

Tool/software: Linux

Hi Sir 

we used SDK 6.0 with uboot version 2013.01 and would like to control SPI CS0 and CS1for different device's data Read/Write.

we set the pin-mux as below in uboot

static struct module_pin_mux spi0_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */

{OFFSET(spi0_cs1), (MODE(0) | RXACTIVE |
PULLUDEN | PULLUP_EN)}, /* SPI0_CS1 */
{-1},
};

and enable SSPI command 

when we execute below command and found the pin signal of CS0 and CS1 has the same behavior.

     sspi 0:0.0 8 1f

Is there any limitation/notices for SPI0 chip-select setting ??

thanks for your help.

BR

Yimin

  • 0
    TI__Guru**** 393215 points
    Hi,

    The software team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Expert 1495 points

    Hi Sir

    we used latest SDK 03.02.00.05 to duplicate this issue in GP-EVM

    set the same configuration as below

    static struct module_pin_mux spi0_pin_mux[] = {

        {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},   /* SPI0_SCLK */

        {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |

                        PULLUDEN | PULLUP_EN)},                    /* SPI0_D0 */

        {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},     /* SPI0_D1 */

        {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |

                        PULLUDEN | PULLUP_EN)},                    /* SPI0_CS0 */

        {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE |

                        PULLUDEN | PULLUP_EN)},                    /* SPI0_CS1 */

        {-1},

    };

    and execute below command

                    sspi 0:0.0 8 1f

                    sspi 0:1.0 8 1f

    CS1 and CS2 has the same behavior. 

    please advise and thanks for your help.

  • 0 in reply to Biser Gatchev-XID
    Expert 1495 points

    Hi Sir

    Do you have any update for this case ? 

    BR

    Yimin

  • 0 in reply to yimin bai1
    TI__Genius 15510 points

    On the GP EVM, how are the profile switches set? If not profile 2, can you change them to profile 2 and test again? From the u-boot code:

                    /* In profile #2 i2c1 and spi0 conflict. */
                    if (profile & ~PROFILE_2)
                            configure_module_pin_mux(i2c1_pin_mux);

    Steve K.

  • 0 in reply to Steve Kipisz
    Expert 1495 points

    Hi Sir 

    We used GP-EVM and set profile2 with latest SDK.

    execute command sspi 0:0.0 8 1f and got below waveform

    do you have any suggestion why CS1 pin will become low-level after execute sspi 0:0.0 8 1f  command ? 

    execute command sspi 0:1.0 8 1f and got below waveform

    do you have any suggestion why CS0 pin will become low-level after execute sspi 0:1.0 8 1f  command ? 

    thanks 

    BR

    Yimin

  • 0 in reply to yimin bai1
    TI__Genius 15510 points

    It looks like the McSPI is configured for multi-channel mode and not single channel mode so both channels get written to. I was able to recreate it here. I dumped the MCSPI_MODULCTRL register, I saw the register value was 0x00000004 so it is in multi-channel mode.

    Steve K.

  • 0 in reply to Steve Kipisz
    Expert 1495 points
    Hi Steve

    thanks for your reply.

    We would like to R/W two SPI devices by using CS0 and CS1 pin.

    it seems there are some problems about CS pin control in SPI driver.

    please let us know what configuration we missed or offer the patch to fix this issue.

    BR
    Yimin
  • 0 in reply to Steve Kipisz
    Expert 1495 points

    Hi Steve

    the initial register value of MCSPI_MODULCTRL is 0x01.

    After execute sspi command , it will be modified to 0x04 automatically.

    if we modify the register value from 0x04 to 0x01, it will be changed to 0x04 after executing sspi command.

    Do you have any suggestion how to modify the driver to fix this issue ? 

    thanks

    BR

    Yimin

  • 0 in reply to yimin bai1
    TI__Genius 15510 points

    Working with a hardware applications engineer, we found a hack to get the waveforms correct. It involves setting the EPOL bit in the chconf registers after a reset. I have attach a git diff file. This should get you moving forward while we talk with our software team about a proper fix.

    Steve K.

    u-boot.diff 
    diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index fe784a00dfb2..099d6d37750d 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -127,6 +127,8 @@ static struct module_pin_mux spi0_pin_mux[] = {
 	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
 	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
 			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{OFFSET(spi0_cs1), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS1 */
 	{-1},
 };
 
@@ -357,7 +359,7 @@ void enable_board_pin_mux(void)
 		/* General Purpose EVM */
 		unsigned short profile = detect_daughter_board_profile();
 		configure_module_pin_mux(rgmii1_pin_mux);
-		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(mmc0_no_cd_pin_mux);
 		/* In profile #2 i2c1 and spi0 conflict. */
 		if (profile & ~PROFILE_2)
 			configure_module_pin_mux(i2c1_pin_mux);
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 85f9e85fd4b9..b2033858126c 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -37,6 +37,11 @@ static void spi_reset(struct omap3_spi_slave *ds)
 				 &ds->regs->sysconfig);
 
 	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
+
+	writel(0x40 | readl(&ds->regs->channel[0].chconf), &ds->regs->channel[0].chconf);
+	writel(0x40 | readl(&ds->regs->channel[1].chconf), &ds->regs->channel[1].chconf);
+	writel(0x40 | readl(&ds->regs->channel[2].chconf), &ds->regs->channel[2].chconf);
+	writel(0x40 | readl(&ds->regs->channel[3].chconf), &ds->regs->channel[3].chconf);
 }
 
 static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
@@ -393,10 +398,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
 	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
 
 	/*if transfer must be terminated disable the channel*/
-	if (flags & SPI_XFER_END) {
+//	if (flags & SPI_XFER_END) {
 		chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
 		omap3_spi_write_chconf(ds,chconf);
-	}
+//	}
 
 	return 0;
 }