RTOS/AM3357: PRU ICSS EtherCAT Slave 1.00.02.01

Patrick Ruf

Genius 4770 points

Part Number: AM3357
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi,

Can someone from TI get the exact value for the following definition constants and variables (using an AM3357):

- CSL_ICSSIEP_CAP_CFG_REG
- ((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussIepRegBase

This constant is used in the following code part of the PRU-ICSS-EtherCAT Slave package:

void bsp_pdi_latch0_control(PRUICSS_Handle pruIcssHandle, Uint8 val)
{
    Uint32 reg_val = HWREG(((PRUICSS_HwAttrs *)(
                                pruIcssHandle->hwAttrs))->prussIepRegBase +
                           CSL_ICSSIEP_CAP_CFG_REG);

    if(val & 0x1)  //Latch0 Pos Edge single shot
    {
        reg_val |= 0x40;
    }

    else
    {
        reg_val &= ~0x40;
    }

    if(val & 0x2)  //Latch0 Neg Edge single shot
    {
        reg_val |= 0x80;
    }

    else
    {
        reg_val &= ~0x80;
    }

    HWREG(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussIepRegBase +
          CSL_ICSSIEP_CAP_CFG_REG) = reg_val;
}

I can't find the values in the package.

Regard,

Patrick

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 David Zaucha over 7 years ago in reply to Biser Gatchev-XID

TI__Expert 7570 points

Hi Patrick

It is defined in the PDK in C:\ti\pdk_am335x_version\packages\ti\csl\src\ip\icss\V1\cslr_icss_iep.h as

/* CAP_CFG_REG */
#define CSL_ICSSIEP_CAP_CFG_REG (0x18U)

David

0 Patrick Ruf over 7 years ago in reply to David Zaucha

Genius 4770 points

Hi David,

Thanks for the path to the definitions. Now as I have this information I'm quite confused about the register offsets for the AM335x SOC. The AM335x TRM tells me the following:

But the file "cslr_icss_iep.h" tells me:

/* GLOBAL_CFG_REG */
#define CSL_ICSSIEP_GLOBAL_CFG_REG                              (0x0U)

/* GLOBAL_STATUS_REG */
#define CSL_ICSSIEP_GLOBAL_STATUS_REG                           (0x4U)

/* COMPEN_REG */
#define CSL_ICSSIEP_COMPEN_REG                                  (0x8U)

/* SLOW_COMPEN_REG */
#define CSL_ICSSIEP_SLOW_COMPEN_REG                             (0xCU)

/* COUNT_REG0 */
#define CSL_ICSSIEP_COUNT_REG0                                  (0x10U)

/* COUNT_REG1 */
#define CSL_ICSSIEP_COUNT_REG1                                  (0x14U)

/* CAP_CFG_REG */
#define CSL_ICSSIEP_CAP_CFG_REG                                 (0x18U)

/* CAP_STATUS_REG */
#define CSL_ICSSIEP_CAP_STATUS_REG                              (0x1CU)

/* CAPR0_REG0 */
#define CSL_ICSSIEP_CAPR0_REG0                                  (0x20U)

/* CAPR0_REG1 */
#define CSL_ICSSIEP_CAPR0_REG1                                  (0x24U)

/* CAPR1_REG0 */
#define CSL_ICSSIEP_CAPR1_REG0                                  (0x28U)

/* CAPR1_REG1 */
#define CSL_ICSSIEP_CAPR1_REG1                                  (0x2CU)

/* CAPR2_REG0 */
#define CSL_ICSSIEP_CAPR2_REG0                                  (0x30U)

/* CAPR2_REG1 */
#define CSL_ICSSIEP_CAPR2_REG1                                  (0x34U)

/* CAPR3_REG0 */
#define CSL_ICSSIEP_CAPR3_REG0                                  (0x38U)

/* CAPR3_REG1 */
#define CSL_ICSSIEP_CAPR3_REG1                                  (0x3CU)

/* CAPR4_REG0 */
#define CSL_ICSSIEP_CAPR4_REG0                                  (0x40U)

/* CAPR4_REG1 */
#define CSL_ICSSIEP_CAPR4_REG1                                  (0x44U)

/* CAPR5_REG0 */
#define CSL_ICSSIEP_CAPR5_REG0                                  (0x48U)

/* CAPR5_REG1 */
#define CSL_ICSSIEP_CAPR5_REG1                                  (0x4CU)

/* CAPR6_REG0 */
#define CSL_ICSSIEP_CAPR6_REG0                                  (0x50U)

/* CAPR6_REG1 */
#define CSL_ICSSIEP_CAPR6_REG1                                  (0x54U)

/* CAPF6_REG0 */
#define CSL_ICSSIEP_CAPF6_REG0                                  (0x58U)

/* CAPF6_REG1 */
#define CSL_ICSSIEP_CAPF6_REG1                                  (0x5CU)

/* CAPR7_REG0 */
#define CSL_ICSSIEP_CAPR7_REG0                                  (0x60U)

/* CAPR7_REG1 */
#define CSL_ICSSIEP_CAPR7_REG1                                  (0x64U)

/* CAPF7_REG0 */
#define CSL_ICSSIEP_CAPF7_REG0                                  (0x68U)

/* CAPF7_REG1 */
#define CSL_ICSSIEP_CAPF7_REG1                                  (0x6CU)

/* CMP_CFG_REG */
#define CSL_ICSSIEP_CMP_CFG_REG                                 (0x70U)

/* CMP_STATUS_REG */
#define CSL_ICSSIEP_CMP_STATUS_REG                              (0x74U)

/* CMP0_REG0 */
#define CSL_ICSSIEP_CMP0_REG0                                   (0x78U)

/* CMP0_REG1 */
#define CSL_ICSSIEP_CMP0_REG1                                   (0x7CU)

/* CMP1_REG0 */
#define CSL_ICSSIEP_CMP1_REG0                                   (0x80U)

/* CMP1_REG1 */
#define CSL_ICSSIEP_CMP1_REG1                                   (0x84U)

/* CMP2_REG0 */
#define CSL_ICSSIEP_CMP2_REG0                                   (0x88U)

/* CMP2_REG1 */
#define CSL_ICSSIEP_CMP2_REG1                                   (0x8CU)

/* CMP3_REG0 */
#define CSL_ICSSIEP_CMP3_REG0                                   (0x90U)

/* CMP3_REG1 */
#define CSL_ICSSIEP_CMP3_REG1                                   (0x94U)

/* CMP4_REG0 */
#define CSL_ICSSIEP_CMP4_REG0                                   (0x98U)

/* CMP4_REG1 */
#define CSL_ICSSIEP_CMP4_REG1                                   (0x9CU)

/* CMP5_REG0 */
#define CSL_ICSSIEP_CMP5_REG0                                   (0xA0U)

/* CMP5_REG1 */
#define CSL_ICSSIEP_CMP5_REG1                                   (0xA4U)

/* CMP6_REG0 */
#define CSL_ICSSIEP_CMP6_REG0                                   (0xA8U)

/* CMP6_REG1 */
#define CSL_ICSSIEP_CMP6_REG1                                   (0xACU)

/* CMP7_REG0 */
#define CSL_ICSSIEP_CMP7_REG0                                   (0xB0U)

/* CMP7_REG1 */
#define CSL_ICSSIEP_CMP7_REG1                                   (0xB4U)

/* RXIPG0_REG */
#define CSL_ICSSIEP_RXIPG0_REG                                  (0xB8U)

/* RXIPG1_REG */
#define CSL_ICSSIEP_RXIPG1_REG                                  (0xBCU)

/* CMP8_REG0 */
#define CSL_ICSSIEP_CMP8_REG0                                   (0xC0U)

/* CMP8_REG1 */
#define CSL_ICSSIEP_CMP8_REG1                                   (0xC4U)

/* CMP9_REG0 */
#define CSL_ICSSIEP_CMP9_REG0                                   (0xC8U)

/* CMP9_REG1 */
#define CSL_ICSSIEP_CMP9_REG1                                   (0xCCU)

/* CMP10_REG0 */
#define CSL_ICSSIEP_CMP10_REG0                                  (0xD0U)

/* CMP10_REG1 */
#define CSL_ICSSIEP_CMP10_REG1                                  (0xD4U)

/* CMP11_REG0 */
#define CSL_ICSSIEP_CMP11_REG0                                  (0xD8U)

/* CMP11_REG1 */
#define CSL_ICSSIEP_CMP11_REG1                                  (0xDCU)

/* CMP12_REG0 */
#define CSL_ICSSIEP_CMP12_REG0                                  (0xE0U)

/* CMP12_REG1 */
#define CSL_ICSSIEP_CMP12_REG1                                  (0xE4U)

/* CMP13_REG0 */
#define CSL_ICSSIEP_CMP13_REG0                                  (0xE8U)

/* CMP13_REG1 */
#define CSL_ICSSIEP_CMP13_REG1                                  (0xECU)

/* CMP14_REG0 */
#define CSL_ICSSIEP_CMP14_REG0                                  (0xF0U)

/* CMP14_REG1 */
#define CSL_ICSSIEP_CMP14_REG1                                  (0xF4U)

/* CMP15_REG0 */
#define CSL_ICSSIEP_CMP15_REG0                                  (0xF8U)

/* CMP15_REG1 */
#define CSL_ICSSIEP_CMP15_REG1                                  (0xFCU)

/* COUNT_RESET_VAL_REG0 */
#define CSL_ICSSIEP_COUNT_RESET_VAL_REG0                        (0x100U)

/* COUNT_RESET_VAL_REG1 */
#define CSL_ICSSIEP_COUNT_RESET_VAL_REG1                        (0x104U)

/* PWM_REG */
#define CSL_ICSSIEP_PWM_REG                                     (0x108U)

/* SYNC_CTRL_REG */
#define CSL_ICSSIEP_SYNC_CTRL_REG                               (0x180U)

/* SYNC_FIRST_STAT_REG */
#define CSL_ICSSIEP_SYNC_FIRST_STAT_REG                         (0x184U)

/* SYNC0_STAT_REG */
#define CSL_ICSSIEP_SYNC0_STAT_REG                              (0x188U)

/* SYNC1_STAT_REG */
#define CSL_ICSSIEP_SYNC1_STAT_REG                              (0x18CU)

/* SYNC_PWIDTH_REG */
#define CSL_ICSSIEP_SYNC_PWIDTH_REG                             (0x190U)

/* SYNC0_PERIOD_REG */
#define CSL_ICSSIEP_SYNC0_PERIOD_REG                            (0x194U)

/* SYNC1_DELAY_REG */
#define CSL_ICSSIEP_SYNC1_DELAY_REG                             (0x198U)

/* SYNC_START_REG */
#define CSL_ICSSIEP_SYNC_START_REG                              (0x19CU)

/* WD_PREDIV_REG */
#define CSL_ICSSIEP_WD_PREDIV_REG                               (0x200U)

/* PDI_WD_TIM_REG */
#define CSL_ICSSIEP_PDI_WD_TIM_REG                              (0x204U)

/* PD_WD_TIM_REG */
#define CSL_ICSSIEP_PD_WD_TIM_REG                               (0x208U)

/* WD_STATUS_REG */
#define CSL_ICSSIEP_WD_STATUS_REG                               (0x20CU)

/* WD_EXP_CNT_REG */
#define CSL_ICSSIEP_WD_EXP_CNT_REG                              (0x210U)

/* WD_CTRL_REG */
#define CSL_ICSSIEP_WD_CTRL_REG                                 (0x214U)

/* DIGIO_CTRL_REG */
#define CSL_ICSSIEP_DIGIO_CTRL_REG                              (0x300U)

/* DIGIO_STATUS_REG */
#define CSL_ICSSIEP_DIGIO_STATUS_REG                            (0x304U)

/* DIGIO_DATA_IN_REG */
#define CSL_ICSSIEP_DIGIO_DATA_IN_REG                           (0x308U)

/* DIGIO_DATA_IN_RAW_REG */
#define CSL_ICSSIEP_DIGIO_DATA_IN_RAW_REG                       (0x30CU)

/* DIGIO_DATA_OUT_REG */
#define CSL_ICSSIEP_DIGIO_DATA_OUT_REG                          (0x310U)

/* DIGIO_DATA_OUT_EN_REG */
#define CSL_ICSSIEP_DIGIO_DATA_OUT_EN_REG                       (0x314U)

/* DIGIO_EXP_REG */
#define CSL_ICSSIEP_DIGIO_EXP_REG                               (0x318U)

What is the right information? For example the register "IEP_TMR_CNT" has an offset of 0xC from the TRM point of view. But in the definitions there is an other regsiter called "SLOW_COMPEN" with this same offset of 0x0C.

Regards,
Patrick

0 Frank Walzer over 7 years ago in reply to Patrick Ruf

TI__Mastermind 43121 points

Patrick,

I think both are correct... but they refer to different versions of ICSS_M. Thee TRM describes what is implemented in AM335x ICSS.

However in AM57x devices we have a newer version of ICSS_M that has more features and as such slightly modified register set too. Now if that is used correctly in the current EtherCAT release that should cover AM335x, Am437x and AM57x at the same time is something that needs to be checked to my mind. This will take a bit of time.

Where did you encounter the issue with the macro? When just compiling TI example or when writing your own app?

It may also be related to changes in the base PDK (CSL...). So it requires to look at the correct versions matching the higher layer SW release requirements.

Regards,

0 Patrick Ruf over 7 years ago in reply to Frank Walzer

Genius 4770 points

Frank,

Right now we do not have an issue with a certain macro.
What I'm doing:
Our EtherCAT slave implementation is based on the lastest AM335x SYSBIOS Industrial SDK V1.1.3.3. I now try to bring this implementation to the newest state of the PRU-ICSS-ETHERCAT-SLAVE V1.0.2.1 from TI. As TI did change the code so is is usabla for other SOC's beside the AM335x this is not an easy task. The source code I mentioned in my first post is a new, so I try to write the code so it is compatible with the register definitions used in the AM335x SYSBIOS Industrial SDK. While doing this I have also tried to check the used register offsets that are already used.

The file "cls_icss_iep.h" is from the folder "...icss\V1" so I assume that this is the definition for the V1 ICSS and if this is the version used in AM335x my opinion is that this should reflect what is implemented in the AM335x. But maybe David gave me the wrong path and it should be "V0" for the AM335x (?). I think those definitions match with the TRM of the AM335x.

Maybe you can shed some light on this topic and tell me what are the right definition files for the AM335x PRU-ICSS.

Regards,
Patrick

0 David Zaucha over 7 years ago in reply to Patrick Ruf

TI__Expert 7570 points

Patrick

I apologize for the misdirection. v0 is correct.

The mapping is done in C:\ti\PRU-ICSS-EtherCAT_Slave_01.00.02.01\examples\board\include\soc_icss_header.h

. Starting at line 69

#if defined(SOC_AM335x) || defined(SOC_AM437x)
#define CSL_ICSSIEP_COUNT_REG0          CSL_ICSSM_IEP_COUNT
#define CSL_ICSSIEP_DIGIO_CTRL_REG      CSL_ICSSM_IEP_DIGIO_CTRL
#define CSL_ICSSIEP_DIGIO_EXP_REG       CSL_ICSSM_IEP_DIGIO_EXP
#define CSL_ICSSIEP_DIGIO_DATA_OUT_REG CSL_ICSSM_IEP_DIGIO_DATA_OUT
#define CSL_ICSSMIIMDIO_LINK            CSL_ICSSM_MII_MDIO_LINK
#endif

It looks like we may be missing

#define CSL_ICSSIEP_CAP_CFG_REG CSL_ICSSM_IEP_CAP_CFG

I will confirm this with the development team

David

0 Patrick Ruf over 7 years ago in reply to David Zaucha

Genius 4770 points

David,

Thanks for this correction. Your last post was very helpful. It would also be extremely helpful if the AM335x TRM would reflect all the available registers from the ICSS and a description of the bits. This would allow us customers to follow and understand the code better. Especially in the case of source code that is visible to us and maybe needs to be altered because of company-owned of source code guidlines and rules.
Maybe you can confirm this also to the documentation team.

Thanks and best regards,
Patrick

0 David Zaucha over 7 years ago in reply to Patrick Ruf

TI__Expert 7570 points

Patrick

Very good. An AM335x TRM update is in process for this that should be released shortly.

David

0 David Zaucha over 7 years ago in reply to David Zaucha

TI__Expert 7570 points

Patrick

The development team confirmed that the definition of
#define CSL_ICSSIEP_CAP_CFG_REG CSL_ICSSM_IEP_CAP_CFG
should be added.

David

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RTOS/AM3357: PRU ICSS EtherCAT Slave 1.00.02.01