Linux/AM5728: VOUT1 jitter issue

Hi Brad,

Thank you for quick reply.

Yes,They use  a 20 MHz main clock.

I'm sorry.
Mention of M4=9 is a mistake.
M4=8 is right.

vout_clk= 20MHz / (39+1)*(2*1800) / (8+1) / 5 =40MHz  

I have our customer try it using the parameter of your answer.

Best Regards,
Shigehiro Tsuda

Hi Brad,

I confirmed it with a value recommended by you.
It does not seem to be the result that is better than a value set in the following.

custom try value:

①N=7
②M=8
③M4=0
④DISPC_DIVISOR　00010001
⑤CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX　0x0

1000 cycle jitter=7.2ns

your recommend value:

①N=122
②M=1968
③M4=7
④DISPC_DIVISOR　00010002
⑤CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX　0x0

1000 cycle jitter=33.2ns

It seems to follow that jitter decreases so that setting of N is smaller.
Will you confirm which value is good again?

There are the following additional questions.

[your answer]
using an odd DISPC_DIVISOR will result in a duty cycle that's not 50%

[add question]
In the case of odd divide, is the module of other peripherals not 50% duty, too?
Is it limitation only for DISPC module?

Best Regards,
Shigehiro Tsuda

shigehiro tsuda said:

I confirmed it with a value recommended by you.
It does not seem to be the result that is better than a value set in the following.

custom try value:

①N=7
②M=8
③M4=0
④DISPC_DIVISOR　00010001
⑤CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX　0x0

1000 cycle jitter=7.2ns

your recommend value:

①N=122
②M=1968
③M4=7
④DISPC_DIVISOR　00010002
⑤CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX　0x0

1000 cycle jitter=33.2ns

It seems to follow that jitter decreases so that setting of N is smaller.
Will you confirm which value is good again?

I'm not sure how you're measuring the jitter.  We used a spectrum analyzer and were able to see less spread when using large N and large M.

There's one other critical detail I missed...  You're using DPLL_VIDEO right now.  Its jitter characteristics are not nearly as good as DPLL_HDMI.  Can you switch to using DPLL_HDMI as your clock source?  If not, we recommend using a clock cleaner between the processor and serdes.

shigehiro tsuda said:

[your answer]
using an odd DISPC_DIVISOR will result in a duty cycle that's not 50%

[add question]
In the case of odd divide, is the module of other peripherals not 50% duty, too?
Is it limitation only for DISPC module?

I don't have an all encompassing list, but I've also seen this on McSPI and QSPI.

Hi Brad,

Thank you for quick reply.

I understood that you confirm by using a spectrum analyzer and were able to see less spread when using large N and large M.

Our customer use a oscilloscope.

This result of mesurring the jitter is the following.

[your answer]
There's one other critical detail I missed...  You're using DPLL_VIDEO right now.  Its jitter characteristics are not nearly as good as DPLL_HDMI.  Can you switch to using DPLL_HDMI as your clock source? 

Our customer use HDMI interface.
I confirm whether VOUT1 is resolution same as HDMI to our customer.

[your answer]
If not, we recommend using a clock cleaner between the processor and serdes.

Is the use of clock cleaner all right only with clock?
Is it not influenced in the timing of hsync,vsync,data?

[your answer]
I don't have an all encompassing list, but I've also seen this on McSPI and QSPI.

Thank you for the information.
When the clocks of other pheripheral are divided with an odd number, I understand that there are the peripheral which is not 50% duty.

Best Regards,
Shigehiro Tsuda

shigehiro tsuda said:

Is the use of clock cleaner all right only with clock?
Is it not influenced in the timing of hsync,vsync,data?

Correct, only clock.

One quick follow-up... Using a clock cleaner will introduce a propagation delay on the clock. You need to correspondingly use one of the alternate timing modes for the interface to get the clock/data properly aligned. I believe this has been done with CDCE813.

Hi Brad,

Thank you for your quick reply.

I will correspond to our customer at following three suggestion.
①Setting in DPLL_VIDEO1 　
②use DPLL_HDMI
③use jitter cleaner of CDCE813

If there is update of the setting of DPLL_VIDEO1 of small jitter, please tell me.
Specifications of the customers include a demand with 1000 cycle jitter as less than 0.5ns.

In addition, how much does jitter of your evaluation result in spectrum analyzers become?

Thank you for your kindly and quick support.

Best Regards,
Shigehiro Tsuda

shigehiro tsuda said:

If there is update of the setting of DPLL_VIDEO1 of small jitter, please tell me.
Specifications of the customers include a demand with 1000 cycle jitter as less than 0.5ns.

DPLL_HDMI is a different type of DPLL and has much better jitter performance.  You would really need to switch to DPLL_HDMI to have any chance of meeting that requirement.

Hi Brad,

Thank you for quick reply.
I understand that the jitter performance has much better by use of DPLL_HDMI.
Our customer confirms whether jitter is revised by use of DPLL_HDMI.
Wait for the confirmation result.

Best Regards,
Shigehiro Tsuda