AM3352: DDR3 errors during continuous access

Hi,

We cannot accept requests for design reviews on this forum. You need to contact TI directly for this. I don't exactly understand what you mean by:

"but after SDRAM_Config register is rewrite, AM335x can access with DDR3 and It can confirm correct value is wrote."

Could you explain in more detail?

What software are they using?

Hi, Biser

Thank you for your reply.
it has error every 0x2000 address of access when Continuously write.
after Continuously write, They try to read, but these value are 0x0000.

but after customer rewrite same value in SDRAM_CONFIG register you know,
AM335x can read Correct value AM335x wrote.

Actually They can make software by themselves, but They see GEL file of SK board and Configuration is almost same.

Best Regards
Hiroyasu

This may be either a wrong connection on the address lines, or wrong configuration of page size. I cannot tell much more based on the information you give. Is this a single board or they see the same issue on multiple boards?

Hi, Biser

Thank you for your reply!
I always apriciate to you !

Customer made 2 board and There have same error both.
I guess customer has wrong configuration.
Because It is O.K. when single access.

Should we change reg_pagesize of SDRAM_CONFIG register you told me ?
Actually This reg_pagesize of description's word means 32bit ?

Best Regards
Hiroyasu

I don't know what memory you are using or what is the schematic configuration. I cannot say.

Hi, Biser

I ask about TRM.
You told me we may have issue pagesize.
I think We should change reg_pagesize bit of SDRAM_CONFIG register.
This understanding correct?

and It is described about PAGE size in TRM below

Can you tell me what bit of word ?
I think this word is 32bit.
This understanding is correct ?

Best Regards
Hiroyasu

Hi, Biser

Thank you for your reply. I got it.

I went to customer's office today.
and I checked their register.

Their value of SDRAM_CONFIG register is 0x61C04B32.
and when they set 0x71C04B32, EMIF/DDR3 is working.
They can read/write 0x2000 or later.
but it is limited, it means it gots error when it write 128MB.
They research more detail.

Actually It depends on REG_IBANK_POS field in the SDRAM Config register.

GEL file's value is 0x61C04AB2

They use this Micron's DDR3 below:

○MT41J128M16JT-125
www.micron.com/.../mt41k256m16ly-107

and SK board support this DDR3 below:

○MT41K256M16LY-107
www.micron.com/.../mt41j128m16jt-125

then I have 2 questions.

(1)Why REG_IBANK_POS vlaue is 0 in GEL file ?
Because SK board's DDR3 parameter is below:
Bank address is 8.
　 I think REG_IBANK_POS should be 4(8 banks).

(2)If my understand is correct, I think REG_IBANK_POS bit field should be 4(8 banks)
Because Customer board's parameter is below:

Best Regards
Hiroyasu

Hiroyasu said:

(1)Why REG_IBANK_POS vlaue is 0 in GEL file ?

See the description of the SDRAM_CONFIG register (section 7.3.5.3 from the TRM):

"Set to 0 to assign internal bank address bits from lower OCP address bits, as shown in the tables for OCP Address to DDR2/3/mDDR Address Mapping"

What is their memory? Your post is self-contradictory. The SK uses 2x8-bit memories. What is this GEL file they are using?

Hi, Biser

SK board is on MT41J128M16JT-125 isn't it ?
It is 16bit device !

and My customer using MT41K256M16LY-107.

www.micron.com/.../mt41k256m16ly-107

Customer can not use GEL file , They use their source code.
but it is almost same SK board GEL.

and This EMIF condiguration tips mention below:

processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips

REG_IBANK_POS - This register sets up the internal bank position. Please see "Address Mapping" section of the TRM for more information. This is typically left at 0 to allow for maximum number of banks to be open and to allow interleaving between them.

why REG_IBANK_POS value typically 0 ?

Best Regards
Hiroyasu

Hi, Biser

I want to know logical Address.

OCP address is described in TRM of Table 7-208 when REG_IBANK_POS=0 and REG_EBANK_POS=0

I understand this means below(EBANK=0):

OCP address is described in TRM of Table 7-210 when REG_IBANK_POS=2 and REG_EBANK_POS = 0

I understand this means like this below(EBANK=0,Row Address=15bit, Colum=10bit):

This understanding is correct?

Best Regards
Hiroyasu

Hi, Biser

I'm sorry. I have a misstake.
I post again.

I want to know logical Address.

OCP address is described in TRM of Table 7-208 when REG_IBANK_POS=0 and REG_EBANK_POS=0

I understand this means below(EBANK=0):

OCP address is described in TRM of Table 7-210 when REG_IBANK_POS=2 and REG_EBANK_POS = 0

I understand this means like this below(EBANK=0,Row Address=15bit, Colum=10bit):

This understanding is correct?

Best Regards
Hiroyasu

Hi, Biser

Thank you for your reply.
I got it.

Best Regards
Hiroyasu