Hi there,
we are using a AM3352 on a custom board that was derived from the Beaglebone. It is using the EMIF with a single MT41K256M16HA-125 Memory Chip. The trace lengths are different to the trace lengths on the Beagleboard. As an SPL we use Uboot to load a Linux Kernel
Due to some errors in the linux device tree file the CPU at first was running with 300Mhz instead of 600Mhz. When the CPU was running with the lower Clock speed there were no Memory issues. With a higher clock speed we noticed that we had some memory issues ( corrupt SCP file transfers, dropped SSH sessions, memtester showed failures, ... ).
We tried to fix this by tuning the DDR3 timings like described in 
But the Salve Ratio Search Programm only shows 0x0 values all the time. Since we use the same memory chip as the Beaglebone we get the same register values for ALLOP_DDR3_SDRAM_TIMING1-3 as used in the example. Only values for DATAx_PHY_RD DQS_SLAVE_RATIO, DATAx_PHY_FIFO_WE_SLAVE_RATIO and DATAx_PHY_WR DQS_SLAVE_RATIO are different.
Could there be another resaon for getting 0x0 values beside wrong register values in the GEL file?
Also:
Since we already have some devices deployed and don't want to update Uboot on deployed devices we thought of using the EMIF Linux Kernel drivers to change register values when we determined the right DDR3 timings. But the EMIF driver doesn't seem to be doing anything with our current Kernel ( 4.4.21 ).
Can the EMIF drivers be used to change memory timings when the kernel is loaded?
Best regards
Edit:
Xenon_CPU-FPGA-Module_RatioSeed.xlsx
BeagleBlack_400Mhz_4GbDDR_new_rev.gel
BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_0.gel
BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_0.log
CortxA8: Output: **** AM335x BeagleBlack Initialization is in progress .......... CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress......... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: DDR PHY Configuration done CortxA8: Output: **** AM335x BeagleBlack Initialization is Done ****************** [CortxA8] Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet 0 Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window 40 Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window 6D Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window 0 *************************************************************** The Slave Ratio Search Program Values are... *************************************************************** PARAMETER MAX | MIN | OPTIMUM | RANGE *************************************************************** DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 *************************************************************** rd_dqs_range = 0 fifo_we_range = 0 wr_dqs_range = 0 wr_data_range = 0 Optimal values have been found!! *************************************************************** The Slave Ratio Search Program Values are... *************************************************************** PARAMETER MAX | MIN | OPTIMUM | RANGE *************************************************************** DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 *************************************************************** ===== END OF TEST =====
BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_1.gel
BeagleBlack_400Mhz_4GbDDR_PHY_INVERT_CLKOUT_1.log
CortxA8: Output: **** AM335x BeagleBlack Initialization is in progress .......... CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress......... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: DDR PHY Configuration done CortxA8: Output: **** AM335x BeagleBlack Initialization is Done ****************** Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet 1 Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window 40 Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window ED Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window 7F *************************************************************** The Slave Ratio Search Program Values are... *************************************************************** PARAMETER MAX | MIN | OPTIMUM | RANGE *************************************************************** DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 *************************************************************** rd_dqs_range = 0 fifo_we_range = 0 wr_dqs_range = 0 wr_data_range = 0 Optimal values have been found!! *************************************************************** The Slave Ratio Search Program Values are... *************************************************************** PARAMETER MAX | MIN | OPTIMUM | RANGE *************************************************************** DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000 *************************************************************** ===== END OF TEST =====
