Hi Sitara support team,
About the Workaround for Errata Advisory 1.0.30,
"Connect the VSS_OSC and VSS_RTC terminals and respective crystal circuit
component grounds directly to the nearest PCB digital ground..."
Q1. Are there reccomended pattern length and impedance value?
Q2. Is there possibility that the internal clock has the influence of such as the noise of the external 25MHz clock?
Best regards,
Kanae