AM5728: Prioritization of memory transactions

John D97

Part Number: AM5728

We will have two MPU cores (A15) running simultaneously, and core 0 task must run in real time, while core 1 task does not have to. We foresee memory transactions to be the bottleneck and we don't want core 1 transactions to inhibit core 0 transactions.
We would like to suspend the task running on core 1 if EMIF FIFOs are full, thus giving core 0 monopoly access to memory for some time. So, is it possible to monitor the current levels of FIFOs on EMIF modules?
Alternative solution might be to prioritize the transactions from core 0, core 1 and DMM, so core 1 transactions will have the lowest priority. I didn't find a way to do it, but maybe there is any?

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Which software SDK is this?

0 John D97 over 7 years ago in reply to Biser Gatchev-XID

Intellectual 540 points

We are using CSL and our custom OS built over it. So, we can access whichever registers we want.

0 John D97 over 7 years ago in reply to Biser Gatchev-XID

Intellectual 540 points

I'm still hoping to get the answer for my question.

0 Rogerio Almeida over 7 years ago in reply to John D97

TI__Mastermind 26025 points

Sorry for the delay...I am checking with apps team...

0 melissaw over 7 years ago in reply to Rogerio Almeida

TI__Genius 15200 points

Hi John,

Are you running the A15 cores in SMP mode (both cores use the same kernel) or AMP mode (both cores run independently)?

Regards,
Melissa

0 John D97 over 7 years ago in reply to melissaw

Intellectual 540 points

AMP. Core 0 runs task(s), which are real-time, while core 1 will run a task, which we can suspend for some time if we need. It is OK to sacrifice the core 1 performance for the sake of core 0, but not vice versa.

0 melissaw over 6 years ago in reply to John D97

TI__Genius 15200 points

Hi John,

There are several registers in the Control Module that set priority for EMIF initiators (i.e. CTRL_CORE_EMIF_INITATOR_PRIORITY_1-7). However, unfortunately the two A15'x look like the same initiator to the bus. They cannot be configured to have independent priorities.

Regards,
Melissa

0 John D97 over 6 years ago in reply to melissaw

Intellectual 540 points

OK, understood.
What about monitoring current levels of FIFOs of the EMIF modules? Is it possible?
If we can monitor levels of FIFOs, then we can suspend core 1 in case FIFOs are full or almost full.
Or maybe you can suggest some other means to achieve the same goal - prioritize core 0 over core 1? They host our custom OS and we have full control over everything.

0 John D97 over 6 years ago in reply to melissaw

Intellectual 540 points

So, is there a way to check the the FIFO levels on the EMIF modules?

0 melissaw over 6 years ago in reply to John D97

TI__Genius 15200 points

Hi John,

There is no mechanism to directly check the EMIF FIFO levels.

However, the EMIF Performance Counters can be configured to count the number of cycles that the FIFO is full. I'm checking if this could possibly be used by the ARM to indirectly monitor the FIFO levels.

Regards,

Melissa

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AM5728: Prioritization of memory transactions