• Resolved

Linux/AM5728: PLL clock setting for 3 video outputs

Part Number: AM5728

Tool/software: Linux

Hi Expert,

We have a board with 3 video outputs on am5728.

dss channel lcd1, vout1 to our hdmi encoder 1.
dss channel tv, hdmi to tpd12s.
dss channel lcd2, vout2 to out hdmi encoder 2.

However, I can't configure clk src correctly.
Dss-pll driver can't set M4 and M6 clock both active.

How to configure video output src clk?
Should I use video2 PLL?

My psdk version is 3.02.05.

Regards,
Hugo


=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x00000282
video1 PLL : Enabled
video2 PLL : Disabled
HDMI PLL : Enabled
DSI1_A_CLK mux : DPLL Video1
DSI1_B_CLK mux : DPLL Video1
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00011001
2: LCD1 clk switch : DSI1_A_CLK
3: LCD2 clk switch : DSI1_B_CLK
10: LCD3 clk switch : DSS clk
1: func clk switch : DSS clk
13: DPI1 output : LCD1

DSS_STATUS (0x5800005C) = 0x01409282

DSI_CLK_CTRL (0x58004054) = 0x80004001

CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040F03

CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00001702

========================================================
Register dump for DPLL video1
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300 | 0x00000018 |
| 0x58004304 | 0x00002603 |
| 0x58004308 | 0x00000000 |
| 0x5800430C | 0x000DEC4E |
| 0x58004310 | 0x00E06008 |
| 0x58004314 | 0x0000000B |
| 0x58004318 | 0x00000000 |
| 0x5800431C | 0x00000000 |
| 0x58004320 | 0x00000000 |
|----------------------------|
Details for DPLL video1
PLL status : Locked
M4 hsdiv(1) : inactive
M5 hsdiv(2) : inactive
M6 hsdiv(3) : Active
M7 hsdiv(4) : inactive

PLL_REGM = 1782
PLL_REGN = 39
M4 DIV = 0
M6 DIV = 11
M7 DIV = 0

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1782000000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 0
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 148500000
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================
Register dump for DPLL hdmi
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58040200 | 0x00000018 |
| 0x58040204 | 0x00000003 |
| 0x58040208 | 0x00000000 |
| 0x5804020C | 0x0003600E |
| 0x58040210 | 0x00602004 |
| 0x58040214 | 0x00001400 |
| 0x58040218 | 0x00000000 |
| 0x5804021C | 0x00000000 |
| 0x58040220 | 0x00040000 |
|----------------------------|
Details for DPLL hdmi
PLL status : Locked
M4 hsdiv(1) : inactive
M5 hsdiv(2) : inactive
M6 hsdiv(3) : inactive
M7 hsdiv(4) : inactive

PLL_REGM = 432
PLL_REGN = 7
M4 DIV = 0
M6 DIV = 0
M7 DIV = 0
PLL_REGM2 = 1
PLL_REGM_F = 1
PLL_SD = 5
HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000
HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000

Clock calculations (DPLL hdmi)
sysclk = 20000000
CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 1080000000

========================================================
Clock O/P of MUXes
DPLL PER H12 Output 192000000
CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204

DSI1_A_CLK : 0
DSI1_B_CLK : 148500000
DSI1_C_CLK : 148500000

DISPC_DIVISOR (0x58001804) = 0x00010001

2: LCD1 clk : 0
3: LCD2 clk : 148500000
10: LCD3 clk : 192000000
1: func clk : 192000000

LCD1 logic clk(/ 1 ) : 0 pix clk(/ 1 ) : 0
LCD2 logic clk(/ 1 ) : 148500000 pix clk(/ 1 ) : 148500000
LCD3 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000