AM5728: Can't compile the DSS example from PDK

Thank you! I successfully compiled the DSS example (and other examples) in Release.

Sounds like I need CCS connected in order to run this example? So far it says

**** PDK SBL ****
**** Copying Application Image to DDR ****

 SD Boot - file open completed successfully

 MPU CPU0 image load completed
Jumping to MPU CPU0 Application...

and hangs. Is there a way to use it without CCS? Like load tigf files from the SD card?

By the way, I could not build in debug mode. I was trying

E:\TI_PDK~1\PDK_AM~1\packages>gmake vps BUILD_PROFILE=debug BOARD=evmAM572x CORE=a15
E:\TI_PDK~1\PDK_AM~1\packages>gmake vps BUILD_PROFILE=debug BOARD=evmAM572x
E:\TI_PDK~1\PDK_AM~1\packages>gmake vps BUILD_PROFILE=debug

and none of them compiles. I suspect I again do something improperly.

We've obtained the XDS200 debugger, got CCS 6.2 and tried to run the DSS example. It starts, outputs some build and board info:

Build time            : [17:36:11 May 10 2017]
FVID2 Version         : [FVID_02_01_00_01]
BSP Version           : [BSP_01_08_00_xx]
Platform              : [EVM]
SOC                   : [AM572X]
SOC Revision          : [ES2.0]
FT Revision           : [5]
Package               : [UNKNOWN]
Core                  : [A15]
Board Detected        : [AM572X GP EVM]
EEPROM Base Board Name: [AM572PM_]
Base Board Revision   : [REV A]
Daughter Card Revision: [REV A]

and then hangs on polling the PLL_STATUS register (0x58004304, DPLL_VIDEO1_MAIN_L3). The PLLCTRL_RESET_DONE is always 0 and processor loops inside the function PMHALVideopllConfigure():

file pmhal_videopll.c:
292: do
293: {
294:     videopllStatus =
295:         PMHALVideopllGetResetStatus(videopllId);
296: } while (0 == videopllStatus);

videopllStatus is always 0, so seems like PLL never comes out of reset. Entire PLL_STATUS register is read as 0.

I'm reminding that we are using the TMDSEVM572x board with LCD module plugged in and PDK 1.0.6. Any suggestions about what might be wrong and how to fix it?

"gmake vps BUILD_PROFILE=debug" still does not work for us. After some time of the building process, it ends up with an error.

Correct, I was able to build in release. Just in case I am attaching my .out file.

Thanks, I appreciate your help.

vps_examples_displayDss_a15_0_release.7z

Hi,

I tested AM572x GP EVM, which has a LCD display mounted. I run the A15 DSS release build, I didn't have any problem. Do you use the GEL to intialize the EVM? Below is my CCS GEL log:

IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.

IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.

IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.

IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.

IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.

CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---

CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz

CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----

CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---

CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----

CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.

CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---

CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---

CortexA15_0: GEL Output: --->>> I2C Init <<<---

CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---

CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---

CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---

CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---

CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...

CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...

CortexA15_0: GEL Output: PER DPLL already locked, now unlocking

CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....

CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...

CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---

CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---

CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---

CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...

CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!

CortexA15_0: GEL Output: Launch full leveling

CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers

CortexA15_0: GEL Output: as per HW leveling output

CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from

CortexA15_0: GEL Output: PHY_STATUSx registers

CortexA15_0: GEL Output: Launch full leveling

CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers

CortexA15_0: GEL Output: as per HW leveling output

CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from

CortexA15_0: GEL Output: PHY_STATUSx registers

CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (2GB total)

CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<---

CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

Then, I loaded the out file and run:

[CortexA15_0] DISP_DSS_APP: Sample Application - STARTS !!!

*** VPDMA Firmware Loading... ***

VPDMA Firmware Address = 0xa0011fc0

VPDMA Load Address = 0x4897d004

VPDMA Firmware Version = 0x4d0001b8

VPDMA List Busy Status = 0x00000000

*** VPDMA Firmware Load Success ***

*** VPDMA Firmware Loading... ***

VPDMA Firmware Address = 0xa0011fc0

VPDMA Load Address = 0x4899d004

VPDMA Firmware Version = 0x4d0001b8

VPDMA List Busy Status = 0x00000000

*** VPDMA Firmware Load Success ***

*** VPDMA Firmware Loading... ***

VPDMA Firmware Address = 0xa0011fc0

VPDMA Load Address = 0x489bd004

VPDMA Firmware Version = 0x4d0001b8

VPDMA List Busy Status = 0x00000000

*** VPDMA Firmware Load Success ***

*** VPDMA Firmware Loading... ***

VPDMA Firmware Address = 0xa0011fc0

VPDMA Load Address = 0x489dd004

VPDMA Firmware Version = 0x4d0001b8

VPDMA List Busy Status = 0x00000000

*** VPDMA Firmware Load Success ***

Build time : [13:41:07 May 25 2017]

FVID2 Version : [FVID_02_01_00_01]

BSP Version : [BSP_01_08_00_xx]

Platform : [EVM]

SOC : [AM572X]

SOC Revision : [ES2.0]

FT Revision : [3]

Package : [UNKNOWN]

Core : [A15]

Board Detected : [AM572X GP EVM]

EEPROM Base Board Name: [AM572PM_]

Base Board Revision : [REV A]

Daughter Card Revision: [REV A]

Load 4 YUV422I_YUYV video frames of size 1920x1080 to location: 0x0x81600000

Trying to Load buffer from SD card.

Couldnot Load buffer from SD card.

waiting for 1 min to load buffer from scripting consolePress any key (in UART console) after loading buffer

loadRaw(0x81600000, 0, "C:\\display_yuyv422_prog_packed_1920_1080.tigf", 32, false);

Attached is my .out file.vps_examples_displayDss_a15_0_release.xa15fg

Can you try if works on your setup? I tried yours, it went to main after load, then went away when I ran.

Regards, Eric

I advanced further. Seems like my problem was GEL files - I was using them improperly, I applied them to the wrong core. Thanks for your GEL log, it showed me my problem.

Now I am getting the message

Load 4 YUV422I_YUYV video frames of size 1920x1080 to location: 0x0x81600000
Trying to Load buffer from SD card.
Couldnot Load buffer from SD card.
waiting for 1 min to load buffer from scripting consolePress any key (in UART console) after loading buffer
loadRaw(0x81600000, 0, "C:\\display_yuyv422_prog_packed_1920_1080.tigf", 32, false);

sometimes it passes further and requests the second file as well:

Load 4 YUV422I_YUYV video frames of size 1920x1080 to location: 0x0x81600000
Trying to Load buffer from SD card.
Couldnot Load buffer from SD card.
waiting for 1 min to load buffer from scripting consolePress any key (in UART console) after loading buffer
loadRaw(0x81600000, 0, "C:\\display_yuyv422_prog_packed_1920_1080.tigf", 32, false);
Load 4 BGR24_888 video frames of size 1920x1080 to location: 0x0x825d2000
Trying to Load buffer from SD card.
Couldnot Load buffer from SD card.
waiting for 1 min to load buffer from scripting consolePress any key (in UART console) after loading buffer
loadRaw(0x825d2000, 0, "C:\\display_bgr888_prog_packed_1920_1080.tigf", 32, false);

How I tried to load the files:
1. Launch my target configuration.
2. Select core a15_0 and pick up gpevm_am572x.gel for it.
3. Connect to the core a15_0.
4. Enter in the console two commands:
loadRaw(0x81600000,0,"C:\\display_yuyv422_prog_packed_1920_1080.tigf",32,false)
loadRaw(0x825d2000,0,"C:\\display_bgr888_prog_packed_1920_1080.tigf",32,false)
No spaces between parameters and no semicolon at the end, per processors.wiki.ti.com/.../Scripting_Console
There is no feedback for such commands, so I waited some time after each to let it load these large files.
5. Reset the CPU.
6. Run/Load the .out file. It runs to the 'main' automatically.
7. Resume the run.
8. It outputs the request for loading file or files, but does nothing afterwards. If I hit "Suspend", stack trace shows that we are inside kernel function Task_exit().

By the way - file name of the second display dump was incorrect.
c:\ti\pdk_am57xx_1_0_6\packages\ti\drv\vps\docs\test_inputs\dss_input_files.rar contains file
display_gbr888_prog_packed_1920_1080.tigf
while suggested console command loads file
display_bgr888_prog_packed_1920_1080.tigf
So I renamed it.

Not sure what happened when you ran my .out file. You say "it went to main after load, then went away when I ran", but what do you mean by "went away"?
For me now your .out and my .out behave more or less in the same way. They request .tigf file or files and then do nothing regardless if I have loaded them previously via console.

I wasn't able to run the DSS example per your instructions. It might be that I was doing something wrong. My problem was that the function, which reads a character from UART, UART_readPolling_v1(), attempts to do it and if there is nothing to read, it waits for 1 ms and then attempts again and etc. But for me, function which waits, UART_osalDelay(), never returns. If suspended, stack trace shows processor inside Task_exit().
I created a workaround. I commented out BspUtils_uartGetChar() call and placed a breakpoint on the following line. Then debugger hits the breakpoint and I load the bitmap via scripting console. And I did the similar thing for the code which asks user for test ID.
This is how I got the DSS example working. I was able to see the video output on either the attached LCD or on HDMI.
Debug build now also works after I have changed the makefile per your advice.
Thank you for your help, I appreciate it.

But now I have another problem.
Our goal is to run this DSS example and figure out how to replicate all initializations and etc. and get the display working for our custom OS. We can't drag entire VPS driver (plus whatever it is dependent on) into our project. And so far we even cannot get the HDMI pixel clock running. We think that what we lack in order to get the pixel clock running, is the two bits in the CM_DSS_CLKSTCTRL register, bits 17 and 18. This register is a status register (read-only) and we must do something to get these two bits to become set. And I was trying to step through the DSS example source code and try lo locate, what particular action pops up these bits.
And I found out that when I run the DSS example under JTAG debugger, these two bits are set once the processor hits main(). But when I run the very same example by itself, these two bits are off. So, there must be some artifact of the JTAG debugger being attached and apparently switching something on the processor.

It might be that DSS example later invokes some driver calls, which reassures that these two bits pop up, but there is no way to figure it out as long as they are set from the beginning already.

I did not 100% trust the "registers" subwindow in CCS and I read this register in code and output its value via UART:

For the free-runnig DSS example, right after main():
cm_dss_clkstctrl = 0x102

For the DSS example, under debugger, right after main():
cm_dss_clkstctrl = 0x61f02

MLO is the same in both cases.

So, how do we set bits 17 and 18 of the CM_DSS_CLKSTCTRL? We managed to set bits 9..12 (cm_dss_clkstctrl = 0x1f02), but it does not turn on the pixel clock after we call vpscore_dctrlHdmiPowerOn(). This is the function, which turns on the HDMI pixel clock as its last action.