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AM3358: McASP subsystem questions

Robert Morse89
Prodigy 30 points
Part Number: AM3358

I am working on a new board using the AM3358 to implement an audio driver using the McASP subsystem, and there are a couple of places where the technical reference manual (Literature number SPRUH73P) is not quite clear.

 Specifically:

1)      What is the purpose of the memory space shown in Table 2-1 McASP0 Data starting at 0x46000000 and McASP1 Data starting at 0x46400000? What is this connected to? How does data get from this space to the McASP?

 

2)      In section 22.3.10.2.1 “AFIFO Data Transmission”, it states “If the host CPU writes to the Write FIFO, independent of a transmit DMA request, the WFIFO will accept host writes until full.”

       Where is the AFIFO? At what address does the CPU write to to accomplish the above?

Thanks!

  • 0
    TI__Guru**** 393215 points
    1) This is the base address of the respective McASP set of registers. You will notice that in the McASP section only the register offsets are given, which should be added to the base address to get the register physical address.

    2) You write data to the XBUF_0 to XBUF_5 registers.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points

    Thank you for your reply. Are you saying that both McASP Data and McASP CFG spaces point to the McASP configuration registers?

    Can you tell me what the difference is between McASP Data at  0x46000000 to 0x463FFFFF (size 4MB)  and  McASP CFG at 0x48038000 to 0x48039FFF (size 8kB)?

    If they both point to the McASP configuration registers, why the difference in the size?

    Thanks for your help.

  • 0 in reply to Robert Morse89
    Prodigy 30 points

    For anyone following this, this is the answer I got from my field application engineer:

    1)      What is the purpose of the memory space shown in Table 2-1 McASP0 Data starting at 0x46000000 and McASP1 Data starting at 0x46400000? What is this connected to? How does data get from this space to the McASP?

     This data space pertains to the FIFO.  Technically, a single 32-bit register would have been sufficient for this.  However, there’s a reason why we dedicated a larger chunk of memory…  In particular, when you look at things such as EDMA efficiency, you get better system throughput for incrementing, contiguous data than you do for a fixed address.  So by allowing the EDMA accesses to increment within that space we end up with better system optimization.  That’s why there’s more than a single address.

     

    2)      In section 22.3.10.2.1 “AFIFO Data Transmission”, it states “If the host CPU writes to the Write FIFO, independent of a transmit DMA request, the WFIFO will accept host writes until full.”

           Where is the AFIFO? At what address does the CPU write to to accomplish the above?

     The AFIFO is accessed at the addresses you mentioned in your first question.  Writes to that address space are going to the transmit FIFO.  Reads from that address space come from the receive FIFO.