• Resolved

CCS/TMDXIDK5718: Target connect error

Part Number: TMDXIDK5718

Tool/software: Code Composer Studio

Hi

 

I made the example projects, with the script in the pdk, for our AM571x IDK (TMDXIDK5718).

The first project I want to start is the “GPIO_LedBlink_idkAM571x_armTestProject”. But when I start it, I get an GEL-Error:

 

Cortex_M4_IPU1_C0: GEL Output: --->>> AM571x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> AM571x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM571x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM571x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP: GEL Output: --->>> AM571x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP: GEL Output: --->>> AM571x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> AM571x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> AM571x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> AM571x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: 	--->>> AM571x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL already locked, now unlocking...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL already locked, now unlocking...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in DONE!
CortexA15_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x4C000060
	 at IODFT_TLGC=*((unsigned int *) (base_addr+0x60U)) [AM571x_ddr_config.gel:201]
	 at AM571x_reset_emif_params_ddr3_666(0x4c000000U) [AM571x_ddr_config.gel:908]
	 at AM571x_DDR3_666MHz_Config() [AM571x_startup_common.gel:40]
	 at OnTargetConnect()


FILE:

GPIO_Blink_Example.zip

It is possible to start debugging, but in the function Board_initGPIO();, it will stay in an infinite loop.

For debugging we use the onboard debugger XDS100V2.

BR

Christoph

 

  • Hi,

    Which software SDK is this - Linux or RTOS?

     

    Best Regards
    Biser
  • In reply to Biser Gatchev-XID:

    Hi

    It is RTOS.

    We use CCS 7.0.0.00043 and pdk_am57xx_1_0_6.

    Best regards

    Christoph
  • In reply to Christoph Waltisberg:

    Thanks. The RTOS team have been notified. They will respond here.

     

    Best Regards
    Biser
  • In reply to Biser Gatchev-XID:

    Hi,

    I tried with an AM5718IDKEVM, CCS7.0, JTAG is Texas Instrumnets xds100v2 on board emulator. Did you select "IDK_AM571X" as the "Board or Device" in target configuration?

    From my connection, I didn't have any issue. My CCS console log is attached idk571x_ccs70.txt. In comparing to yours, it looks several domains DPLL is already locked, the GEL unlocking it and reprogram it, including DDR:

    CortexA15_0: GEL Output:    DDR DPLL already locked, now unlocking....

    You can't reprogram DDR DPLL so you have the error. Do you start CCS connection from a fresh power cycle of the board? Do you have any thing running on SOC already (e.g, a SD card inserted with Linux or SDK RTOS MLO bootloader)? Please remove SD card if so.

    Regards, Eric

  • Chris,

    The issue you are reporting is not caused by the GPIO LED example but some issue that iss preventing your DDR from being initialized correctly from the CCS based GEL files. As Eric explained this could be caused due to code already existing in DDR (from SD boot or some other boot mode) or could be caused due to some issue with DDR timing configuration/board issue.

    Please provide the Boot switch setting and ensure that no SD card is inserted in the microSD slot. Also, ensure that you are following the steps provided here:
    processors.wiki.ti.com/.../TMDXIDK5728_Hardware_Setup

    Regards,
    Rahul

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  • In reply to Rahul Prabhu:

    Hi Rahul and Eric

    Thank you for your quick answer.

    I will give you a feedback, on monday.

    Best regards

    Christoph