Other Parts Discussed in Thread: AM5728
We are using AM5726 Sitara processor in our design with 27 MHz crystal on SYSCLK1. We are using latest Processor-SDK-LINUX-AM57x_03_03_00_04. SYSBOOT[9:8] pins are configured properly to reflect 27MHz input. We having problem to bring up the SPL U-boot.
We are currently using CCSv7 to troubleshoot spl boot loader.I manually has modified CCSv7 AM572x_prcm_config.gel to support 27MHz crystal and able to load/execute spl and test programs from SRAM or DDRAM. AM5728 DPLL configuration has a lot of parameters and generate a lot of subclocks.
My question is - Does TI has a AM5728 GEL reference file with dplls clock setting for 27 MHz (AM572x_prcm_config.gel that is coming with CCS is supporting only 20 MHz crystal clock see below):
#define SYS_CLK1 (20)
/******************************************************************************
* dpll_a15_opp_config() : Cortex A15 DPLL OPP configurations
******************************************************************************/
dpll_a15_opp_config(uint32_t OPP, uint32_t DEVICE_TYPE)
{
uint32_t dpll_m, dpll_n, divm2, dcc_en;
dcc_en = 0;
GEL_TextOut("\tCortex A15 DPLL OPP %d clock config is in progress...\n",,,,, OPP);
if(OPP_HIGH == OPP)
{
//1500MHz at 20MHz sys_clk
dpll_m = 600;
dpll_n = 7;
divm2 = 1;
dcc_en = 1;
}
else if(OPP_OD == OPP)
{
//1176MHz at 20MHz sys_clk
dpll_m = 294;
dpll_n = 4;
divm2 = 1;
}
else //default to OPP_NOM
{
//1000MHz at 20MHz sys_clk
dpll_m = 500;
// dpll_m = 370;
dpll_n = 9;
divm2 = 1;
}
if (CM_IDLEST_DPLL(CM_CLKMODE_DPLL_MPU)&0x1)
{
GEL_TextOut("\tCortex A15 DPLL is already locked, now unlocking... \n");
dpll_unlock_sequence(CM_CLKMODE_DPLL_MPU);
}
CM_CLKSEL_DPLL(CM_CLKMODE_DPLL_MPU) = ((dpll_m << 8) | dpll_n | (dcc_en << 22));
// Program DPLL_CLKOUT divider (M2 = 1)
CM_DIV_M2_DPLL(CM_CLKMODE_DPLL_MPU) = divm2;
dpll_lock_sequence(CM_CLKMODE_DPLL_MPU);
GEL_TextOut("\tCortex A15 DPLL OPP %d is DONE!\n",,,,, OPP);
}
/******************************************************************************
* dpll_per_opp_config() : PER DPLL OPP configurations
*****************************************************************************/
dpll_per_opp_config(uint32_t OPP, uint32_t DEVICE_TYPE)
{
GEL_TextOut("\tPER DPLL OPP %d clock config in progress...\n",,,,, OPP);
if (CM_IDLEST_DPLL(CM_CLKMODE_DPLL_PER)&0x1)
{
GEL_TextOut("\tPER DPLL already locked, now unlocking \n");
dpll_unlock_sequence(CM_CLKMODE_DPLL_PER);
}
/* CM_CLKSEL_DPLL_PER DPLL MULT */
CM_CLKSEL_DPLL(CM_CLKMODE_DPLL_PER) = 0x6004;
/* CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIV = 4*/
CM_DIV_M2_DPLL(CM_CLKMODE_DPLL_PER) = 0x4;
/* CM_DIV_M3_DPLL_PER.DPLL_CLKOUT_DIV = 3 */
CM_DIV_M3_DPLL(CM_CLKMODE_DPLL_PER) = 0x1;
/* CM_DIV_H11_DPLL_PER.HSDIVIDER_CLKOUT1_DIV = 3 */
CM_DIV_H11_DPLL(CM_CLKMODE_DPLL_PER) = 0x3;
/* CM_DIV_H12_DPLL_PER.HSDIVIDER_CLKOUT2_DIV = 4 */
CM_DIV_H12_DPLL(CM_CLKMODE_DPLL_PER) = 0x4;
/* CM_DIV_H13_DPLL_PER.HSDIVIDER_CLKOUT2_DIV = 4 : To get 192M output */
CM_DIV_H13_DPLL(CM_CLKMODE_DPLL_PER) = 0x04;
/* CM_DIV_H14_DPLL_PER.HSDIVIDER_CLKOUT3_DIV = 2 */
CM_DIV_H14_DPLL(CM_CLKMODE_DPLL_PER) = 0x2;
dpll_lock_sequence(CM_CLKMODE_DPLL_PER);
GEL_TextOut("\tPER DPLL OPP %d is DONE!\n",,,,, OPP);
}
/******************************************************************************
* dpll_core_opp_config() : CORE DPLL OPP configurations
*****************************************************************************/
dpll_core_opp_config(uint32_t OPP, uint32_t DEVICE_TYPE)
{
GEL_TextOut("\tCORE DPLL OPP %d clock config is in progress...\n",,,,, OPP);
if (CM_IDLEST_DPLL(CM_CLKMODE_DPLL_CORE)&0x1)
{
GEL_TextOut("\tCORE DPLL OPP already locked, now unlocking.... \n");
dpll_unlock_sequence(CM_CLKMODE_DPLL_CORE);
}
// Program L3 & L4 dividers from CORE DPLL
/* L3 clock = CORE CLK /2; L4 clock = L3 clock /2; CORE_CLK=CORE_X2_CLK/2 */
WR_MEM_32(CM_CLKSEL_CORE, 0x110);
/* Lock and code outputs ARE overriden */
WR_MEM_32(CM_DLL_CTRL, 0x00000000);
/* CM_CLKSEL_DPLL_CORE.PLL_MULT = 0x200 */
CM_CLKSEL_DPLL(CM_CLKMODE_DPLL_CORE) = 0x10a04;
/* CM_DIV_M2_DPLL_CORE */
CM_DIV_M2_DPLL(CM_CLKMODE_DPLL_CORE) = 0x2;
/* CM_DIV_M3_DPLL_CORE */
CM_DIV_M3_DPLL(CM_CLKMODE_DPLL_CORE) = 0x1;
/* CM_DIV_H12_DPLL_CORE */
CM_DIV_H12_DPLL(CM_CLKMODE_DPLL_CORE) = 0x4;
/* CM_DIV_H13_DPLL_CORE */
CM_DIV_H13_DPLL(CM_CLKMODE_DPLL_CORE) = 0x3E;
/* CM_DIV_H14_DPLL_CORE */
CM_DIV_H14_DPLL(CM_CLKMODE_DPLL_CORE) = 0x5;
/* CM_DIV_H22_DPLL_CORE */
CM_DIV_H22_DPLL(CM_CLKMODE_DPLL_CORE) = 0x5;
/* CM_DIV_H23_DPLL_CORE */
CM_DIV_H23_DPLL(CM_CLKMODE_DPLL_CORE) = 0x4;
/* CM_DIV_H24_DPLL_CORE */
CM_DIV_H24_DPLL(CM_CLKMODE_DPLL_CORE) = 0x6;
dpll_lock_sequence(CM_CLKMODE_DPLL_CORE);
GEL_TextOut("\tCORE DPLL OPP %d is DONE!\n",,,,, OPP);
}
I also have checked U-boot source code and there is no settings for 27MHz crystal in the arch/arm/cpu/armv7/omap5/hw_data.c. (see below)
/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
To properly setup dplls the following clocks are required:
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
.gmac = gmac_dpll_params_2000mhz,
};
Does TI can provide reference settings for all this clock either in for of GEL file or hw_data.c for 27 MHz crystal clock on the SYSCLK1.
Does also changes from AM572x with 27MHz crystal on SYSCLK1 forum post is required to support 27 MHz clock.
Please let me know.
Thank you in advance.
Best regards,
Andriy Nazar
