Other Parts Discussed in Thread: AM3352
we are on round 2 of making custom boards using the AM3352. we don't have them yet but in the mean time we are using the beagle bone black board as a dev board to work out some of the kinks we couldn't quite figure out with the last hardware. some details:
Yes i am using the beagle bone black gel file
this is an RTOS project, NOT LINUX, we are not doing LINUX.
however this code is all running in MAIN so we have not hit RTOS yet, there shouldn't really be any interaction with RTOS
we are using init code that is mostly custom.
i soldered on the JTAG header to the BBB board, i can connect and emulate in CCS v6.2 just fine
YES i know in order to see the registers you have to have all your clocks up and running.
YES i have seen the clock tree tool and i am using it
on to the problem. i found the code to enable the clocks in one of the SDK examples so my code is based on that. here is the code:
enableModule(CM_PER_LCDC_CLKCTRL,
CM_PER_LCDC_CLKSTCTRL,
CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK);
where enableModule is defined as:
void enableModule(volatile U32 *clkCtrlReg, volatile U32 *clkStCtrlReg, U32 clkActMask)
{
/* Enable the module */
*clkCtrlReg = PRCM_MODULEMODE_ENABLE;
/* Check for module enable status */
while(PRCM_MODULEMODE_ENABLE != (*clkCtrlReg & PRCM_MODULEMODE_MASK));
/* Check clock activity - ungated */
while(clkActMask != (*clkStCtrlReg & clkActMask));
/* Check idle status value - should be in functional state */
while((PRCM_MODULE_IDLEST_FUNC << PRCM_IDLE_ST_SHIFT) != (*clkCtrlReg & PRCM_IDLE_ST_MASK));
}
after i run this i do not have control of the LCDC registers. they all show up as ???????? in memory and "Error: unable to read" in the registers window
when i start poking around the clocks i see that CLKACTIVITY_LCDC_L4_OCP_GCLK is inactive, but the module is considered enabled and the other clock is considered active. when i try to find which clock that would be i kind of hit a roadblock because there isn't anything in the tech manual (spruh731.pdf ) that is called that. when i go to the LCDC section of spruh731.pdf i see that there are 3 clocks to deal with, and the OCP clocks are L3, so that implies that the functional clock is the L4 clock, even though the clock that is inactive is called OCP in the register window. since none of that makes any sense i tried to go to the clock tree tool. when i go to the clock tree tool and try and figure out which clock is disabled after i enable the module i find that it is the pixel clock. when i try to enable the pixel clock i get caught at a gate whose status is read at CM_DIV_M5_DPLL_CORE, the gate that stays "gated" is ST_HSDIVIDER_CLKOUT2_GATE_CTRL. the gate is set to auto. i thought that auto meant that if something is enabled that uses that clock source it will enable itself but there doesn't seem to be anything i can do to ungate this clock. granted, i am thinking that the pixel clock might not prevent me from accessing the registers but i could be wrong.
so i am a bit lost. i don't know what register and what clock setting i need to enable the LCD registers. i can't really blame hardware since the BBB board is already known to work so there is obviously something extra that i didn't enable or mux or something.
i have looked at the LCD_app_raster project but i don't really see what i need to do different based on that project