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AM3359: LCDC register access issues

Part Number: AM3359
Other Parts Discussed in Thread: AM3352

we are on round 2 of making custom boards using the AM3352. we don't have them yet but in the mean time we are using the beagle bone black board as a dev board to work out some of the kinks we couldn't quite figure out with the last hardware. some details:

Yes i am using the beagle bone black gel file

this is an RTOS project, NOT LINUX, we are not doing LINUX.

however this code is all running in MAIN so we have not hit RTOS yet, there shouldn't really be any interaction with RTOS

we are using init code that is mostly custom. 

i soldered on the JTAG header to the BBB board, i can connect and emulate in CCS v6.2 just fine

YES i know in order to see the registers you have to have all your clocks up and running.

YES i have seen the clock tree tool and i am using it

on to the problem. i found the code to enable the clocks in one of the SDK examples so my code is based on that. here is the code:

enableModule(CM_PER_LCDC_CLKCTRL,
CM_PER_LCDC_CLKSTCTRL,
CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK);

where enableModule is defined as:

void enableModule(volatile U32 *clkCtrlReg, volatile U32 *clkStCtrlReg, U32 clkActMask)
{
/* Enable the module */
*clkCtrlReg = PRCM_MODULEMODE_ENABLE;
/* Check for module enable status */
while(PRCM_MODULEMODE_ENABLE != (*clkCtrlReg & PRCM_MODULEMODE_MASK));
/* Check clock activity - ungated */
while(clkActMask != (*clkStCtrlReg & clkActMask));
/* Check idle status value - should be in functional state */
while((PRCM_MODULE_IDLEST_FUNC << PRCM_IDLE_ST_SHIFT) != (*clkCtrlReg & PRCM_IDLE_ST_MASK));
}

after i run this i do not have control of the LCDC registers. they all show up as ???????? in memory and "Error: unable to read" in the registers window

when i start poking around the clocks i see that CLKACTIVITY_LCDC_L4_OCP_GCLK is inactive, but the module is considered enabled and the other clock is considered active. when i try to find which clock that would be i kind of hit a roadblock because there isn't anything in the tech manual (spruh731.pdf ) that is called that. when i go to the LCDC section of spruh731.pdf i see that there are 3 clocks to deal with, and the OCP clocks are L3, so that implies that the functional clock is the L4 clock, even though the clock that is inactive is called OCP in the register window. since none of that makes any sense i tried to go to the clock tree tool. when i go to the clock tree tool and try and figure out which clock is disabled after i enable the module i find that it is the pixel clock. when i try to enable the pixel clock i get caught at a gate whose status is read at CM_DIV_M5_DPLL_CORE, the gate that stays "gated" is ST_HSDIVIDER_CLKOUT2_GATE_CTRL. the gate is set to auto. i thought that auto meant that if something is enabled that uses that clock source it will enable itself but there doesn't seem to be anything i can do to ungate this clock.  granted, i am thinking that the pixel clock might not prevent me from accessing the registers but i could be wrong.

so i am a bit lost. i don't know what register and what clock setting i need to enable the LCD registers. i can't really blame hardware since the BBB board is already known to work so there is obviously something extra that i didn't enable or mux or something. 

i have looked at the LCD_app_raster project but i don't really see what i need to do different based on that project

  • The RTOS team have been notified. They will respond here.
  • Is this problem different from the previous post below?  Note the sequence i had to use to ensure proper access to the LCD module using CCS.

    Regards,

    James

  • no it isn't different but what you suggest doesn't seem to help. trying what you suggest: i enable the functional clock as shown in the original post (and verify the clock control register is 2), i tried adding in code to enable to the lcd clocks in the lcd module registers but part of the problem that i didn't add is that when i try to write to the LCD controller registers is that i get a system abort situation and i end up in _exit. when i try to add *0x4830e006c to my expression window i get "Target Failed to read..." error

    are there other clocks that i need to enable before the LCD controller functional clock? i must be missing something

  • i guess things that do not help is the number of names these clocks have. i have a hard time cross referencing them between the clock tree tool, the tech manual, and the register view.

    in the tech manual we have 2 clocks
    PD_PER_LCD_L3_GCLK (OCP clock)
    PD_PER_LCD_GCLK (functional clock) - no mention of L4

    which do not cross with anything else in the tech manual even though in the comments on the next page it states "From PRCM"

    and you go to the PRCM in the tech manual and you get 2 clocks
    CLKACTIVITY_LCDC_L4_OCP_GCLK (functional clock? in the LCD section it said the L3 was OCP so this must be functional, right?)
    CLKACTIVITY_LCDC_L3_OCP_GCLK (OCPclock?)

    and you go to the clock tree tool and you get 3 clocks
    LCD_GCLK (pixel clock?)
    LCD_L4S_GCLK (functional clock?)
    LCD_L3_GCLK (OCP clock?)

    and of course the registers view share the name with the PRCM in the tech manual.

    when things have 3 different names it gets difficult to track them down from one document/tool to another.
  • so i guess i was implementing it wrong. i never disconnected the power supply from the board before i tried your fix (duh, head slapper there), so the problem was always there when i tried it. now that i power cycled i was able to do what you say, program the registers, load the palette, and move on. i can even see the registers.
  • OK, glad you got it working. I will look into cleaning up the clock names in the TRM.

    To help you out with the clocks (using LCD as an example, but this is true for any module), start with the intergration section at the beginning of each chapter (for LCD, it is section 13-2). This will tell you which clocks are used by the module. For LCD, there are 2 interface clocks and 1 functional clock. Generally anything with an 'L3' or 'L4' in the name is an interface clock. Also, anything with 'OCP' is an interface clock . Anything else is typically a functional clock. So,

    LCD_L3_GCLK (or LCDC_L3_OCP_GCLK) is the master interface clock to the LCD, used when the LCD is a master during data transfers to the display, for example
    LCD_L4_GCLK (or LCDC_L4_OCP_GCLK) is the slave interface clock to the LCD. L4 is just a div by 2 of L3. This is used typically for configuration of the module
    LCD_GCLK is the functional clock of the LCD module, used to clock the functional logic of the module itself.

    Regards,
    James