AM4376: U-boot issue

Part Number: AM4376

Hi,

I have a AM4376 based custom board with UART5 as debug console and with only one 16 bit DDR3 interface.

SDK Details:

=========

ti-processor-sdk-linux-am437x-evm-03.03.00.04-Linux-x86-Install.bin

u-boot-2016.05+gitAUTOINC+4db46a6bbd-g4db46a6bbd

Loaded the u-boot after the  spl ERROR message using JTAG and CCS , but  not getting any u-boot logs. 

we required your help  to resolve the issue

I made the below changes in u-boot

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 4618470bad..ae2c3c7dfb 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -305,6 +305,8 @@ static void rtc32k_enable(void)
 }
 #endif
 
+
+#if 0
 static void uart_soft_reset(void)
 {
     struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
@@ -323,6 +325,27 @@ static void uart_soft_reset(void)
     writel(regval, &uart_base->uartsyscfg);
 }
 
+#endif
+
+#define UART5_BASE_ADD 0x481AA000
+static void uart_soft_reset(void)
+{
+    struct uart_sys *uart_base = (struct uart_sys *)UART5_BASE_ADD;
+    u32 regval;
+
+    regval = readl(&uart_base->uartsyscfg);
+    regval |= UART_RESET;
+    writel(regval, &uart_base->uartsyscfg);
+    while ((readl(&uart_base->uartsyssts) &
+        UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+        ;
+
+    /* Disable smart idle */
+    regval = readl(&uart_base->uartsyscfg);
+    regval |= UART_SMART_IDLE_EN;
+    writel(regval, &uart_base->uartsyscfg);
+}
+
 static void watchdog_disable(void)
 {
     struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 117a63e7ad..832eba6a43 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -55,11 +55,21 @@ void setup_clocks_for_console(void)
 {
     u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
 
+#if 0
     /* Do not add any spl_debug prints in this function */
     clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
             CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
             CD_CLKCTRL_CLKTRCTRL_SHIFT);
+#endif
+
+        idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+        clkctrl = MODULE_CLKCTRL_IDLEST_DISABLED;
+        clrsetbits_le32(&cmper->l4lsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+        CD_CLKCTRL_CLKTRCTRL_SHIFT);
 
+
+#if 0
     /* Enable UART0 */
     clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
             MODULE_CLKCTRL_MODULEMODE_MASK,
@@ -72,6 +82,22 @@ void setup_clocks_for_console(void)
         idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
              MODULE_CLKCTRL_IDLEST_SHIFT;
     }
+#endif
+
+
+    /* Enable UART5 */
+    clrsetbits_le32(&cmper->uart5clkctrl,
+    MODULE_CLKCTRL_MODULEMODE_MASK,
+    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+    MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+    while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+    (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+    clkctrl = readl(&cmper->uart5clkctrl);
+    idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+    MODULE_CLKCTRL_IDLEST_SHIFT;
+ }
+
 }
 
 void enable_basic_clocks(void)
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index 3ffa8e016e..b7d47daa08 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -200,7 +200,7 @@
             reg-shift = <2>;
             interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
             ti,hwmods = "uart6";
-            status = "disabled";
+/*            status = "disabled"; */
         };
 
         mailbox: mailbox@480C8000 {
diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index 142bfc52a1..eaa64527f2 100644
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -22,10 +22,11 @@
     aliases {
         display0 = &lcd0;
         serial3 = &uart3;
+        serial5 = &uart5;
     };
 
     chosen {
-        stdout-path = &uart0;
+        stdout-path = &uart5;
         tick-timer = &timer2;
     };
 
@@ -414,6 +415,13 @@
             0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
         >;
     };
+
+    uart5_pins: uart5_pins {
+        pinctrl-single,pins = <
+            0xd8 ( PIN_INPUT_PULLUP | MUX_MODE4 ) /* (C17) dss_data14.uart5_rxd */
+            0x144 (PIN_OUTPUT_PULLUP | MUX_MODE3 )  /* (A16) rmii1_ref_clk.uart5_txd */
+    >;
+ };
 };
 
 &i2c0 {
@@ -614,6 +622,12 @@
     pinctrl-0 = <&uart3_pins>;
 };
 
+&uart5 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart5_pins>;
+};
+
 &usb2_phy1 {
     status = "okay";
 };
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index 36ecb302c1..9f004d0bed 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -10,4 +10,5 @@ ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
 obj-y    := mux.o
 endif
 
+obj-y    := mux.o
 obj-y    += board.o
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 1db23968f2..bb45ef31fe 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -173,6 +173,7 @@ const struct emif_regs emif_regs_lpddr2 = {
     .emif_cos_config            = 0x000FFFFF
 };
 
+#if 0
 const struct ctrl_ioregs ioregs_ddr3 = {
     .cm0ioctl        = DDR3_ADDRCTRL_IOCTRL_VALUE,
     .cm1ioctl        = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
@@ -183,7 +184,21 @@ const struct ctrl_ioregs ioregs_ddr3 = {
     .dt3ioctrl        = DDR3_DATA0_IOCTRL_VALUE,
     .emif_sdram_config_ext    = 0xc163,
 };
+#endif
+
+//DDR3 16 bit changes
+const struct ctrl_ioregs ioregs_ddr3 = {
+    .cm0ioctl        = DDR3_ADDRCTRL_IOCTRL_VALUE,
+    .cm1ioctl        = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+    .cm2ioctl        = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+    .dt0ioctl        = DDR3_DATA0_IOCTRL_VALUE,
+    .dt1ioctl        = DDR3_DATA0_IOCTRL_VALUE,
+    .dt2ioctrl        = DDR3_DATA0_IOCTRL_VALUE,
+    .dt3ioctrl        = DDR3_DATA0_IOCTRL_VALUE,
+    .emif_sdram_config_ext    = 0x0002c163,
+};
 
+//DDR3 16 bit changes
 const struct emif_regs ddr3_emif_regs_400Mhz = {
     .sdram_config            = 0x638413B2,
     .ref_ctrl            = 0x00000C30,
@@ -232,6 +247,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
     .emif_cos_config        = 0x000FFFFF
 };
 
+#if 0
 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
     .sdram_config            = 0x638413B2,
@@ -255,6 +271,37 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = {
     .emif_cos_config        = 0x000FFFFF
 };
 
+#endif
+
+//DDR3 16 bit changes
+
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+    .sdram_config            = 0x61A052B2,
+    .ref_ctrl            = 0x00000C30,
+    .sdram_tim1            = 0xEAAAD4DB,
+    .sdram_tim2            = 0x266B7FDA,
+    .sdram_tim3            = 0x107F8678,
+    .read_idle_ctrl            = 0x00050000,
+    .zq_config            = 0x50074BE4,
+    .temp_alert_config        = 0x0,
+    .emif_ddr_phy_ctlr_1        = 0x0e084008,
+    .emif_ddr_ext_phy_ctrl_1    = 0x08020080,
+    .emif_ddr_ext_phy_ctrl_2    = 0x00000066,
+    .emif_ddr_ext_phy_ctrl_3    = 0x00000091,
+    .emif_ddr_ext_phy_ctrl_4    = 0x000000B9,
+    .emif_ddr_ext_phy_ctrl_5    = 0x000000E6,
+    .emif_rd_wr_exec_thresh        = 0x80000405,
+    .emif_prio_class_serv_map    = 0x80000001,
+    .emif_connect_id_serv_1_map    = 0x80000094,
+    .emif_connect_id_serv_2_map    = 0x00000000,
+    .emif_cos_config        = 0x000FFFFF
+};
+
+
+//DDR3 16 bit changes
+
 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
     .sdram_config            = 0x638413b2,
     .sdram_config2            = 0x00000000,
@@ -509,7 +556,8 @@ void scale_vcores(void)
 
 void set_uart_mux_conf(void)
 {
-    enable_uart0_pin_mux();
+//    enable_uart0_pin_mux();
+    enable_uart5_pin_mux();
 }
 
 void set_mux_conf_regs(void)
@@ -590,6 +638,7 @@ u32 rtc_only_get_board_type(void)
 
 void sdram_init(void)
 {
+#if 0
     /*
      * EPOS EVM has 1GB LPDDR2 connected to EMIF.
      * GP EMV has 1GB DDR3 connected to EMIF
@@ -616,6 +665,12 @@ void sdram_init(void)
         config_ddr(400, &ioregs_ddr3, NULL, NULL,
                &ddr3_idk_emif_regs_400Mhz, 0);
     }
+#endif
+//DDR3 16 bit changes
+        enable_vtt_regulator();
+        config_ddr(0, &ioregs_ddr3, NULL, NULL,
+               &ddr3_emif_regs_400Mhz_production, 0);
+//DDR3 16 bit changes
 }
 #endif
 
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 3f93d13727..a6218b9ca7 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -60,4 +60,5 @@ static inline int board_is_evm_12_or_later(void)
 void enable_uart0_pin_mux(void);
 void enable_board_pin_mux(void);
 void enable_i2c0_pin_mux(void);
+void enable_uart5_pin_mux(void);
 #endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index f26b21e869..f776f4f4d6 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -21,7 +21,7 @@ static struct module_pin_mux rmii1_pin_mux[] = {
     {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},    /* RMII1_RXDV */
     {OFFSET(mii1_crs), MODE(1) | RXACTIVE},        /* RMII1_CRS_DV */
     {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},    /* RMII1_RXERR */
-    {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},    /* RMII1_refclk */
+//    {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},    /* RMII1_refclk */
     {-1},
 };
 
@@ -53,6 +53,12 @@ static struct module_pin_mux uart0_pin_mux[] = {
     {-1},
 };
 
+static struct module_pin_mux uart5_pin_mux[] = {
+    {OFFSET(lcd_data14), (MODE(4) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+    {OFFSET(rmii1_refclk), (MODE(3) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+    {-1},
+};
+
 static struct module_pin_mux mmc0_pin_mux[] = {
     {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},  /* MMC0_CLK */
     {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* MMC0_CMD */
@@ -120,6 +126,11 @@ void enable_uart0_pin_mux(void)
     configure_module_pin_mux(uart0_pin_mux);
 }
 
+void enable_uart5_pin_mux(void)
+{
+    configure_module_pin_mux(uart5_pin_mux);
+}
+
 void enable_board_pin_mux(void)
 {
     configure_module_pin_mux(mmc0_pin_mux);
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 7b18ffafc7..8c2396bfe0 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -6,10 +6,12 @@ CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
+#CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+#CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL6,CONS_INDEX=6"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -60,3 +62,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_CMD_TIME=y
 CONFIG_DM_I2C=y
+CONFIG_OF_EMBED=y
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index f805c21f26..0dcce72318 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -79,6 +79,7 @@
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM1        0x44e09000    /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM6     0x481aa000 /* Base custom board has UART5 */
 
 #define CONFIG_ENV_IS_IN_FAT
 #define FAT_ENV_INTERFACE        "mmc"
@@ -246,7 +247,7 @@
     "bootpart=0:2\0" \
     "bootdir=/boot\0" \
     "bootfile=zImage\0" \
-    "console=ttyO0,115200n8\0" \
+    "console=ttyO5,115200n8\0" \
     "partitions=" \
         "uuid_disk=${uuid_gpt_disk};" \
         "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \

Thanks in advance.

The code changes seems okay. Maybe the DDR timing are not suitable. Have all the tests succeeded?