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AM5728: FIFO not available on McASP[3:1]

wolfgang gaerber
Intellectual 615 points
Part Number: AM5728

Hi !

Reading AM57xx reference manual (Rev I) - I found following note on page 6165:

"McASP1, McASP2, and McASP3, whose data port are accessible directly via L3_MAIN, do
not support FIFO/constant addressing modes. Incrementing transfers must be used instead."

Well, the idea of the data port is that I can access the serializers using the fifo with a single address.

As there are no other registers on the data port - the notation of incrementing transfers on it would be something I exclude.

So this basically means that data ports via L3_MAIN does not work !!!???

So the only way would be to use the edma with the CFG port without fifo.

In my case (only one channel) this would still be a non-incrementing access.

Or are there undocumented "shadow" addresses of the serializers at DATA port location !!??

rgds,

Wolfgang

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 46712 points

    For access to the McASP FIFOs via the McASP_DAT address range, the least significant bits of the address bus are not used.  For example, for McASP2 as long as the EDMA transactions stay within the 4 MByte address range at 0x45Cx_xxxx then the head/tail of the FIFO will be accessed.  That way you can use the "Increment" mode of the EDMA and still access the McASP FIFO.

    The L3_MAIN memory map in Ch2 shows the full range:

    Regards,
    Kyle

  • 0 in reply to kcastille
    Intellectual 615 points

    Hi Kyle,

    So there is a synchronization problem between McASP and EDMA on L3_MAIn or similar ?

    Today I tried  to operate the fifo thru McASP1_DAT address (no increments) using dsp1 memory writes.

    That works pretty well -

    I could operate the McASP with 44.1kHz fullduplex from 1ms task without any problem.

    Do you know what latency/waitstates are involved on accessing RX/TXBUF(DATA) and fifo-status ?

    In some setups - stuffing the fifo with the dsp could be an interesting option,...

    rgds.

    Wolfgang

  • 0 in reply to wolfgang gaerber
    Intellectual 615 points
    ... or to bring it at the point - if this is a desired behavior - it should be described in the reference manual. If this is an errata - it should be described in the errata. A note which does not describe the problem and points to a vague solution is a problem.
  • 0 in reply to wolfgang gaerber
    TI__Mastermind 46712 points

    Wolfgang,

    The "issue" is not with accessing the same address repeatedly.  Instead, the issue is related to the internal bus protocol of the SoC when "bursts" are issued by the CPU or DMA. 

    Normally a burst is issued with a single address with the burst type set to "increment".  This is the only mode supported on the L3 port for the McASP1/2/3 targets.

    When the DSP is accessing the McASP it is using single word read/writes with "increment" flag (but since it's single word the "increment" concept is irrelevant).

    When the EDMA accesses the McASP, you can set the AMODE to Increment or Const/FIFO.  When issuing a Const/FIFO burst the protocol is intended to access the same word location repeatedly.  Since this is not enabled on that L3 port, you should instead use Increment and since the ls-address bits incrementing still accesses the FIFO ... it works.

    Regards
    Kyle