RTOS/AM5728: Question about shared memory usage

Hi,

I've notified the RTOS team. Their feedback will be posted here.

Best Regards,
Yordan

Hi,

I don't understand you data path fully. Is below correct?
- ARM received data via PCIE
- ARM parses the data, and send it to DSP
- DSP processes the data, and sends it back to ARM
- ARM sends it out via PCIE

"They would like to use OCMC_RAM2 and RAM3 as shared memory for each PCIe-ARM and ARM-DSP."=========> OCMC_RAM3 I understand this is shared between ARM and DSP. What do you mean that OCMC_RAM2 is shared between PCIE and ARM? Do you mean use this region to receive/send data from/to PCIE?

Regards, Eric

Hi Eric,

lding said:

I don't understand you data path fully. Is below correct?
- ARM received data via PCIE
- ARM parses the data, and send it to DSP
- DSP processes the data, and sends it back to ARM
- ARM sends it out via PCIE 

Yes, the data path you described is right.

lding said:

"They would like to use OCMC_RAM2 and RAM3 as shared memory for each PCIe-ARM and ARM-DSP."=========> OCMC_RAM3 I understand this is shared between ARM and DSP. What do you mean that OCMC_RAM2 is shared between PCIE and ARM? Do you mean use this region to receive/send data from/to PCIE?

Yes.

For the performance manner, would you please share the example source codes?
And would you share the IPC Latency measurements documents for AM5728 if you have?

Thanks
Ernest

Hi,

Thanks for the info! I looped in our IPC expert for this questions.

Regards, Eric

Ernest,

You can find the IPC ex02_messageq example in the ipc_3_x/examples/DRA7XX_linux_elf or DRA7XX_bios_elf depending on host ARM OS, which demonstrates the data transfer between ARM and DSP.

For IPC benchmarking, please refer to processors.wiki.ti.com/.../IPC_BenchMarking

Regards,
Garrett

Hi Garrett,
For the Message Q IPC Benchmarking link you guided,
I need to check there has benchmark for TI-RTOS, because the link is for Linux, Android and QNX whereas my customer uses TI-RTOS only.

Regards,
Ernest

Hi Ernest,

For IPC benchmark on TI-RTOS, essentially the customer need port the benchmark Linux host application ipc_3_x/linux/src/tests/MessageQBench.c
referring ipc_3_x/examples/DRA7XX_bios_elf/ex02_messageq/host.
The slave side binary is the same as indicated in the benchmarking wiki: The slave-side binary (messageq_single.x<suffix>), is located in the $(IPC_ROOT)/packages/ti/ipc/tests/bin/<device> directory.

Regards,
Garrett

Hi Garrett,
I understood IPC benchmark need to port on the Linux.

But I have another questions regarding my initial question.
1. For OCMC_RAM2 and OCMC_RAM3 region, can it be possible as below operations simultanuously?
- ARM read/write OCMC_RAM2 operation and DSP read/write OCMC_RAM3 operation at the same time?
2. When I see the "TDAxx Vision SDK SW architecture overview" documents, it shows "IPC performance" which measured latency for each core.
Does AM5728 have similar performance data?
Thanks.

Ernest,

1. OCMC_RAM2 and OCMC_RAM3 region are associated with separate memory controller and connect to L3 interconnect, see the Figure 14-1 Interconnect Overview in TRM. There is no conflict to access OCMC_RAM2 from ARM and OCMC_RAM3 from DSP.

2. We don't have the IPC bechmarking data for each core running RTOS. Since the IPC software package is the same for TDAxx and AM572x, let me check if VisionSDK team have put the benchmarking code in an external repository.

Regards,
Garrett