• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 100 subscribers
  • Views 1280 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM4372: Viewing L2 cache data in CCS

Sh.Sasaki
Guru 13625 points
Part Number: AM4372
Other Parts Discussed in Thread: SYSBIOS

Hi,

I would like to read the value of L2 cache using CCS.
However, when looking at 0x40500000 with the CCS memory browser, it becomes "???".

I think that L2 is enabled because I am executing the following program.

MMUConfigAndEnable();
CACHEEnable(CACHE_IDCACHE, CACHE_INNER_OUTER);

What should I do to read L2?

Best regards,
sasaki

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software are you running?
  • 0 in reply to Biser Gatchev-XID
    Guru 13625 points

    Hi,

    Thank you for your reply.

    I'm using led blink example (C:\ti\pdk_am437x_1_0_8\packages\ti\starterware\examples\gpio\led_blink).

    Best regards,

    sasaki

  • 0 in reply to Sh.Sasaki
    TI__Guru* 95265 points
    Hi,

    MMUConfigAndEnable();
    CACHEEnable(CACHE_IDCACHE, CACHE_INNER_OUTER);

    Those two are the common code for enable MMU and setup caches for many test application. When using CACHE_INNER_OUTER flag, pl310 enables it as cache. If you don't enable L2 as cache, are you able to see the 0x40500000 via CCS?

    Regards, Eric
  • 0 in reply to lding
    TI__Guru* 95265 points
    Hi,

    Some trials:
    The L2 setting as cache or SRAM is controlled by CTRL_MPU_L2 Register (0x44e1_01e0) BIT 16. When SOC out of reset, this default setting is 256KB cache, from CCS I was not able to see the 0x4050_0000. (????? in the window). If I change above register to enable L2 cache as SRAM, I was able to see the 0x4050_0000.

    Then I reset the SOC, and run the typical Sitara examples (like Gpio blink), with the MMUConfigAndEnable() and CACHEEnable(CACHE_IDCACHE, CACHE_INNER_OUTER); Those set-up the L2 cache, I was not able to see the 0x4050_0000 in CCS (???? in the window). I am not sure if this CCS issue or not, still looking into it.

    Regards, Eric
  • 0 in reply to lding
    Guru 13625 points
    Hi lding-san,

    Thank you for investigating.
    Please let me know about progress.

    Best regards,
    Sasaki
  • 0 in reply to lding
    Guru 13625 points
    Hi Eric-san,

    Is this a CCS problem or a device side problem?
    Please let me know if you have progress.

    Best regards,
    Sasaki
  • 0 in reply to Sh.Sasaki
    TI__Guru* 95265 points
    Hi,

    In Processor SDK RTOS, we also have a way to enable or disable cache and configure L2 as RAM or not using SYSBIOS:

    var Cache = xdc.useModule('ti.sysbios.family.arm.a9.Cache');
    Cache.enableCache = true;
    Cache.configureL2Sram = false;//DDR build

    With L2, I was able to see it in CCS memory window. With cache, I can't see it. I believe this is a CCS issue.

    Regards, Eric
  • 0 in reply to lding
    Guru 13625 points
    Hi Eric-san,

    Thank you for your support.
    In case of CCS problem, please let me know in this thread if you know when this problem will be fixed.

    Best regards,
    Sasaki