Hello,
I'd like to know about IPU Cache and AMMU setting. CM4 needs to access the L3/L4 peripherals at high speed in our system. Please refer to the following thread.
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/638925/2360149
How should I configure the CACHE_MMU_XXXXX_POLICY_n register for page setting of the peripherals area? I don't understand some parameters.
bit 19) L1_WR_POLICY -> 0x0: Write through
bit 18) L1_ALLOCATE -> 0x0: No writes are allocated
bit 17) L1_POSTED -> 0x1: Posted
bit 16) L1_CACHEABLE -> 0x0: Non-cacheable
bit 7) EXCLUSION -> Which is the proper setting, 0 and 1?
bit 6) PRELOAD -> Which is the proper setting, 0 and 1?
bit 5) READ -> The area is not read only. But There is no description, 0 and 1.
bit 4) EXECUTE -> The area is not executable. But There is no description, 0 and 1.
bit 3) VOLATILE -> Which is the proper setting, 0 and 1?
bit 1) SIZE -> It depends.
bit 0) ENABLE -> 0x1: Page enabled
Regards,
Kazu