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AM5716: IPU cache and MMU settings

Genius 5785 points
Part Number: AM5716

Hello,

I'd like to know about IPU Cache and AMMU setting. CM4 needs to access the L3/L4 peripherals at high speed in our system. Please refer to the following thread.

https://e2e.ti.com/support/arm/sitara_arm/f/791/p/638925/2360149

How should I configure the CACHE_MMU_XXXXX_POLICY_n register for page setting of the peripherals area? I don't understand some parameters.

bit 19) L1_WR_POLICY -> 0x0: Write through
bit 18) L1_ALLOCATE -> 0x0: No writes are allocated
bit 17) L1_POSTED -> 0x1: Posted
bit 16) L1_CACHEABLE -> 0x0: Non-cacheable
bit 7) EXCLUSION -> Which is the proper setting, 0 and 1?
bit 6) PRELOAD -> Which is the proper setting, 0 and 1?
bit 5) READ -> The area is not read only. But There is no description, 0 and 1.
bit 4) EXECUTE -> The area is not executable. But There is no description, 0 and 1.
bit 3) VOLATILE -> Which is the proper setting, 0 and 1?
bit 1) SIZE -> It depends.
bit 0) ENABLE -> 0x1: Page enabled

Regards,
Kazu

  • The factory team have been notified. They will respond here.
  • Hello,

    I tested on the attached CCS project file. This project is based on the following source files. Since the DDR area for executing program is set as the cache target area by AMMU setting, this program controls GPIO and blinks LED on the board at high speed.

    C:\ti\pdk_am57xx_1_0_8\packages\ti\csl\example\gpio\gpio_toggle\main.c
    C:\ti\pdk_am57xx_1_0_8\packages\ti\csl\example\pcie\write_loopback\pcie_app.c

    I'd like to know the AMMU setting to access to the peripheral area at high speed. So, I set some parameters of 0th large page mapping which configure the page of the peripheral area. However, it seems that the caching for DDR area by 1th large page mapping becomes not able to be applied, because the program blinks LED slowly.

    I measured the processing time of the delay function with SCTM function of Breakpoints.
    https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/p/641731/2373027

    1. uni-cache disabled: 480 million cycles

    2. uni-cache enabled: 15 million cycles
      AppUtilsConfigIPU1DefaultAMMU();
      UNICACHEEnable(CSL_IPU_IPU1_UNICACHE_MMU_CONF_REGS_REGS);

    3. uni-cache enabled and posted write enabled: 480 million cycles
      pagePolicyParams.l1PostedWrite = AMMU_L1_POSTED_WRITE_ENABLED;

    4. uni-cache enabled, posted write enabled and cache enabled: 480 million cycles
      pagePolicyParams.l1PostedWrite = AMMU_L1_POSTED_WRITE_ENABLED;
      pagePolicyParams.l1CacheEnable = AMMU_L1_CACHE_ENABLED;

    Please give me some advice.

    Regards,
    Kazu

    AM571xIDK_IPU_AMMU to E2E.zip