From the AM571x (SR 2.0, 1.0) and AM570x (SR 2.0) Sitara™ Processors Silicon Errata (www.ti.com/.../sprz436d.pdf):
i922 Usability of ECC Feature in the DDR Controller is Limited
and From AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware UG (Rev. A)（www.ti.com/.../sprui97a.pdf ）
5.1 DDR3L SDRAM
。。。The SDRAM implemented on the EMIF on the IDK EVM contains two 4Gbit (256M × 16) SDRAMs for a total of 1GB of DDR3L SDRAM memory。。。
The EMIF also contains an SDRAM attached to the ECC byte lane.
and My undertand is: there are three three 4Gbit(256*16)SDRAMS on the IDK EVM, and the SDRAM attached to the ECC byte lane no need to be used because Errata i922.
so If I want to design my board with 8Gbit SDRAMS, I just need use two 4Gbit SDRAMS on the EMIF ,and no need to attach an SDRAM to the ECCbyte lane. is that right?
About the ECC, I don't understand ,How to decide to disable ECC or enable ECC?
