AM3359: RTOS Timer3 reload issue

Hello Biser,

A week as passed.  When should we expect a reply?

Six months ago you responded (with a question) to a similar post.  What was the resolution to:

https://e2e.ti.com/support/arm/sitara_arm/f/791/t/603947?tisearch=e2e-sitesearch&keymatch=TCRR

Regards,

-david

Thank you.  Please indicate when we could expect a reply.

Hi David,

The designer is looking into your questions, but it may take a few days.

Regards,

Melissa

Hi David,

Sorry for the delays.  The designer has provided the following feedback to your main question, , as well as some follow-up questions.  

>> Q: Under what circumstances could the DMTimer, configured in AR timer mode clocked at 25MHz, fail to reload TCRR with TLDR?

Reading the RTL, logically speaking the counter functions (in priority order) as follows:

1. Resets when reset is asserted

2. Gets loaded when writing to TCRR

3. Reloaded from TLDR when

a. Writing to TTGR

b. AR=1, Counter rollover and Not ClearCmd *

c. Clear when ClearCmd *

d. Count when Counter Enable and Prescaler rollover

* ClearCmd is issued when TCLR.ST=1, TCLR.AR=0 and Counter rollover.

Follow-up questions:

1. How are you configuring AutoReload?  This state is achieved from ‘stop’ by writing TCLR.ST=1 and TCLR.AR=1 at the same time.  Are you sure you’re in ‘stop’ before moving to AutoReload?

2. How can you tell that the TCRR fails to reload?

3. Are you writing to TTGR to reload TCRR?

Regards,

Melissa

Melissa,

Thank you for your reply.  Here are the answers to your follow-up questions:

1. We're using TI SYSBIOS:

    Timer_Params timerParams;
    Timer_Params_init(&timerParams);
    timerParams.extFreq.lo = 24000000;
    timerParams.extFreq.hi = 0;
    timerParams.period = NXT_CLK_REFERENCE_COUNTS;  // Nominally 50
    timerParams.periodType = Timer_PeriodType_COUNTS; //Timer_PeriodType_MICROSECS
    timerParams.startMode = Timer_StartMode_USER;
    nxtClkTimer = Timer_create(1,stepIO_HwIsr,&timerParams,NULL); //TimerID1 at runtime => HWTIMER3

I haven't had a chance to trace through TI's timer code to answer your question directly.

2. The timer is configured to generate a 500kHz interrupt.  The ISR uses this SW 'tick' to count and generate motor clks.  We know the timer ISR failed to be called because the motor stops moving and we can see the timer counter's value is outside the expected range.  The fact that the motor starts moving again in approx three minutes leads us to deduce AR failed -- it take 2.8 minutes to count up from 0x0000_0000 to 0xFFFF_FFFF after which the ISR is working again.

3. No, SW is not writing to TTGR (or any timer register again, after initial setup).

Hi Melissa,

Under real-life load, the issues occurs with a frequency once per day, to once per three days.  It hasn't yet been reproduced "on the bench."

A vendor's board/PCB.  We're aware of Advisory 1.0.30, but it's difficult to implement satisfactorily with this, shall I say, sub-optimal layout -- a respin is required.  The RTC 32,768 Hz xtal osc is not used, DMTimer 3 is driven from the internal PLL, and that is driven by a 24MHz xtal (Sitara's xtal osc).  I did try a simple test enabling the 4x prescaler, but that didn't help.  I have no idea how it's implemented, but my hope was if this is caused by osc noise, the prescaler might act as a metastability synchronizer, but alas.

Regards,

-david