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TMDSEVM572X: DSP program loaded and run from local memory

Part Number: TMDSEVM572X

Looking over the example code that comes with theTMDSEVM572X  EVM, I notice that all DSP execution occurs from L3 memory. L2  is not loaded with the program.

Do you have examples of, or at least guidance for building DSP code that will be loaded into local memory and then loading it at boot-up, particularly in the ARM Linux environment?

  • The software team have been notified. They will respond here.
  • Hi, Richard,

    Please refer to the following documents:
    RTOS software developer's guide,
    processors.wiki.ti.com/.../Processor_SDK_RTOS_Software_Developer_Guide
    IPC User's Guide,
    processors.wiki.ti.com/.../IPC_Users_Guide

    For IPC under Linux environment:
    Processor SDK Linux IPC: http,
    processors.wiki.ti.com/.../Processor_SDK_Linux_IPC
    Linux IPC on AM57xx,
    processors.wiki.ti.com/.../Linux_IPC_on_AM57xx
    Running IPC Examples on DRA7xx/AM572x,
    processors.wiki.ti.com/.../AM572x.

    Hope these documents are helpful.

    Rex
  • Thanks for your speedy reply.

    As it happens, I have been playing with many of the examples you mention and I note that according to the cmd files available and the *.map files which linking produces, you are running the DSP code out of layer 3 memory. Hey, what could go wrong?

    So, I have delved a bit farther into things and I cannot find an instance where the example code actually loads the code into DSP private L2 memory. Is that so? And of so, do you have a very good reason for so doing?

    I am thinking that this has not been attempted by your example developers for the AM572x set-up, but I hope I am wrong.

    I imagine that the loading isn't much beyond a simple move from L3 to L2 initiated by a reset to the DSP followed by a series of memoves, but of course the linked addresses for run time are going to be quite different. Ti tools are good at distinguishing load and runtime addresses and this must be done somewhere, but where? The makefiles I have are linking to load and execute in the same place, up on layer 3. Not optimal for speed of execution, a crucial requirement of my project.

    To complicate matters when I consult your file ~/pdk_am57xx_1_0_8/packages/ti/csl/soc/am572x/src/hw_ctrl_core.h, I find this

    #define CTRL_CORE_CONTROL_DSP1_RST_VECT                                                                     (0x45cU)
    #define CTRL_CORE_CONTROL_DSP2_RST_VECT                                                                     (0x460U)

    Yet when I look at the tech reference, AM572x Sitara Technical Reference Manual, I see this

    CTRL_CORE_CONTROL_DSP1_RST_VECT RW 32 0x0000 055C 0x4A00 255C
    CTRL_CORE_CONTROL_DSP2_RST_VECT RW 32 0x0000 0560 0x4A00 2560

    The good news is, I do not see this macro used in any 'C' modules. But you can understand my reluctance to undertake writing a bootloader, before I see an example where somebody actually made this work in the target I am using.

    So I ask again for a somewhat more specific answer to my problem, do you have any AM572x examples where the DSP L2 memory is loaded with code and .cinit before execution proceeds ?

  • Hi Richard,

    I'm not sure why our examples don't run code out of L2. My guess is it's because of size constraints, many of our examples probably won't fit into L2.

    If you want to move code to L2, you need to change the config file in your project. I've attached one of our I2C examples that I modified to run out of L2 for reference. If you're running out of room in L2, you can use OCMC which should still be faster than using external memory.

    I2C_BasicExample_evmAM572x_c66xExampleProject.zip

    Are you using IPC? If so, you will need to make similar changes to codeMemory/dataMemory in the project's config.bld file.

    I hope this answers your question. Please let us know if it doesn't. 

    Regards,

    Sahin