Linux/AM5728: PCIe configuration in dual-lane mode

Hi, Yongjun,

yes, it is configured as PCIe_SS1 x1. Please refer to Documentation/devicetree/bindings/pci/ti-pci.txt and designware-pcie.txt for device tree binding configuration.

Rex

Thanks for your repy,Rex,we read the documents you mentioned,just find thant config the propertity" num-lanes = <2>"; but after we configed like this,it doesn't work, and the ep device cann't be linked up,the log ouput as follows:

[ 0.597215] ldousb: supplied by VMAIN
[ 0.600699] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[ 0.604076] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges:
[ 0.604086] No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus]
[ 0.604119] IO 0x20003000..0x20012fff -> 0x00000000
[ 0.604141] MEM 0x20013000..0x2fffffff -> 0x20013000
[ 0.634735] dra7-pcie 51000000.pcie_rc: link is not up
[ 0.634919] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00
[ 0.634933] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.634943] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 0.634953] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[ 0.635380] PCI: bus0: Fast back to back transfers disabled
[ 0.635503] PCI: bus1: Fast back to back transfers enabled
[ 0.635587] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[ 0.635604] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[ 0.635617] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 0.635943] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[ 0.695374] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[ 0.698514] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 301, base_baud 0
[ 1.629506] console [ttyS2] enabled

so ,iput the commond lspci -n,the ep cann't be find.is there othere place should be modify?

Hi, Yongjun,

I just checked on AM5728 GP EVM. The default configuration is already x2. It is shown in LnkCap with width x2. I have a x1 pcie card, so the LnkSta shows only Width x1. AM572x-idk and am5728 GP EVM uses the same pcie configuration in dra7.dtsi.

00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 438
Region 0: Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
Region 1: Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: 20200000-202fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000ae124000 Data: 0000
Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Kernel driver in use: pcieport

01:00.0 Network controller: Intel Corporation Centrino Wireless-N 1000 [Condor Peak]
Subsystem: Intel Corporation Centrino Wireless-N 1000 BGN
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 470
Region 0: Memory at 20200000 (64-bit, non-prefetchable) [size=8K]
Capabilities: [c8] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 00000000ae124000 Data: 0001
Capabilities: [e0] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 unlimited
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <128ns, L1 <32us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr+ BadTLP+ BadDLLP+ Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
Capabilities: [140 v1] Device Serial Number e0-94-67-ff-ff-1b-01-e0
Kernel modules: iwlwifi

Hi,Rex,
You mean "LnkCap: Port #0, Speed 5GT/s, Width x2" is two lane is working on the RC? if this is right,the LnkSta should be Width x2,right? because In oure case we use the Xilinx FPGA ipcore to generate the x2 EP,the EP code is ok.
I ask for help from the forum by someone who configed RC x2 successfuly ,he told us should modify " num-lanes = <1>" to "num-lanes = <2>".
but after we modified like this,the ep cann't be emunated.

the follow is x1 log output.

root@am57xx-evm:~# lspci -vv
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal )
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Ste+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort--
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 435
Region 0: Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
Region 1: Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: 20200000-202fffff
Prefetchable memory behind bridge: 20300000-203fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort--
BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3ho)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000add2b000 Data: 0000
Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupport+
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransP-
LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latens
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActiv-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRS-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBF-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, O-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModified-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplet-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualiza-
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Kernel driver in use: pcieport

01:00.0 RAM memory: Xilinx Corporation Default PCIe endpoint ID
Subsystem: Xilinx Corporation Default PCIe endpoint ID
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Ste-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort--
Interrupt: pin A routed to IRQ 467
Region 0: Memory at 20200000 (64-bit, non-prefetchable) [disabled] [siz]
Region 2: Memory at 20200800 (32-bit, non-prefetchable) [disabled] [siz]
[virtual] Expansion ROM at 20300000 [disabled] [size=1M]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3ho)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [60] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 1, Latency L0s unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowW
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupport-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransP-
LnkCap: Port #0, Speed 2.5GT/s, Width x2, ASPM L0s, Exit Latencd
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActiv-
Capabilities: [100 v1] Device Serial Number 00-00-00-01-01-00-0a-35

Hi, Yongjun,
Sorry for the delayed response. I was checking internally. In addition to modifying the num-lanes to 2, could you try also enable pcie2_phy in the evm dtsi file. That is not to touch dra7.dtsi, but overwrite the configuration in the evm dts file. For example, for AM5728 GP EVM, it is am57xx-evm-reva3.dts


+&pcie2_phy {
+ status = "okay";
+};
+
+&pcie1_rc {
+ num-lanes = <2>;
+ phys = <&pcie1_phy>, <&pcie2_phy>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+};

Rex

Hi,Rex,thanks for you replay,did you test as bove? we modify the dts as you mentioned ,but the pcie LnkSta is always x1 by the command lspci.

Hi, Yongjun,

I only have AM5728 GP EVM which has only 1 lane connector. The x2 support was verified on other TI platform, dra76 evm.

Rex

Thanks Rex,we will try, and expect someone can help us simultaneously.