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Linux/AM3352: GPMC multiple read issue

Part Number: AM3352

Tool/software: Linux

Hi all:

In my design, AM335x's GPMC indirecty connected to a SRAM with the help of a MVB device, the MVB device can receive the CS, WR, RD signal from GPMC bus, and then decide to send the CS, WR, RD signal to SRAM.

I config the GPMC to be non-multiplexed attached device connected, 16 bit, use wait1 input pin, read/write asynchronous, and set the timings as long as possible because the connect is indirectly, we must slow the speed.

After all below action, I can read and write the SRAM by single, also get the right timing sequence by oscilloscope, and get the right address line value and data line value , BUT!!!!!!!

If I act a cover test to the SRAM, such as write 0xFFF to all the address of the SRAM, and then read them all, Always I cannot get the desired result, sometimes I found the read value is wrong but when I read the same address manually, I found the return read value is RIGHT! 

At first, I guess the interval between read/wirte access is to short, then I set the register CYCLE2CYCLEDELAY to 15, and enable CYCLE2CYCLEDIFFCSEN and CYCLE2CYCLESAMECSEN, but the modify action seems useless, I can found the read/write period is up to 2us which is long enough, but still get the same result, I have been trapped in the problem for almost half a month , please help me!! Thanks a lot!

  • Hi,

    I don't see how we can help you based on this information. We don't have the hardware to replicate your use case and we do not know how you are doing the test.
  • Thanks for your reply, my core question is : is there any issue can influence the continuous GPMC read/write when the single GPMC read/write action all right? Or is there any other people meet the same condition similar to mine?


    My continous GPMC read/write test code is as bellow:

    for(iTestStep=0;iTestStep<4;iTestStep++)
    {
    for(iAddrLoop=WRTEST_START_ADDR; iAddrLoop < (WRTEST_START_ADDR + MVBSRAM_MEMSIZE); iAddrLoop += 2)
    {
    // prepare data
    memset(aucWriteBuf, 0, 2);

    aucWriteBuf[1] = (usWriteValue[iTestStep] & 0x00FF);
    aucWriteBuf[0] = (usWriteValue[iTestStep] & 0xFF00)>>8;

    // write
    write(fdTargetDev, &aucWriteBuf, iAddrLoop);
    usleep(100);
    }
    usleep(2000000);
    for(iAddrLoop=WRTEST_START_ADDR; iAddrLoop < (WRTEST_START_ADDR + MVBSRAM_MEMSIZE); iAddrLoop += 2)
    {
    memset(aucReadBuf, 0, 2);
    // read
    read(fdTargetDev, &aucReadBuf, iAddrLoop);
    usleep(100);
    read(fdTargetDev, &aucReadBuf, iAddrLoop);
    if((aucReadBuf[1] != (usWriteValue[iTestStep] & 0x00FF)) || \
    (aucReadBuf[0] != (usWriteValue[iTestStep] & 0xFF00)>>8))
    {
    printf("error in addr 0x%x!\n",iAddrLoop);
    printf("\t read data H is 0x%x\r\n", aucReadBuf[1]);
    printf("\t read data L is 0x%x\r\n", aucReadBuf[0]);
    }
    // usleep(1000);
    }

    printf("finish the sram test step %d\n",iTestStep);
    }

    My single GPMC read/write test code is as bellow:

    /*
    Function Name : MvbSram_WriteTest
    */
    void MvbSram_WriteTest(int fdTargetDev)
    {
    unsigned char tempbuff[2] = {0};

    int iWriteAddr, iWriteValue;

    printf("\r\nplease input write addr:");

    scanf("%x", &iWriteAddr);

    printf("\r\nplease input write value:");

    scanf("%x", &iWriteValue);

    printf("\r\nstart to write value 0x%x to addr 0x%x.\r\n", iWriteValue, iWriteAddr);

    tempbuff[0] = (char)(iWriteValue & 0x00FF);
    tempbuff[1] = (char)((iWriteValue & 0xFF00)>>8);

    // write
    write(fdTargetDev, &tempbuff, (size_t)iWriteAddr);

    return;
    }

    /*
    Function Name : MvbSram_ReadTest
    */
    void MvbSram_ReadTest(int fdTargetDev)
    {
    unsigned char tempbuff[2] = {0};

    int iReadAddr, iReadValue;

    printf("\r\nplease input read addr:");

    scanf("%x", &iReadAddr);

    printf("\r\nstart to read value from addr 0x%x.\r\n", iReadAddr);

    read(fdTargetDev,&tempbuff,(size_t)(iReadAddr));
    iReadValue = (int)((tempbuff[0] & 0x00FF) | ((tempbuff[1] & 0x00FF)<<8));

    // read
    printf("\r\nthe returned read value from addr 0x%x is 0x%x.\r\n", iReadAddr, iReadValue);

    return;
    }
  • No, we haven't heard of any issues with continuous GPMC reads. A lot of customers use the GPMC for XIP boot, which is exactly that. Please check your test programs, especially for data type mismatches.
  • Is it because of the intermediate MVB device(a chip)? I am told the timings should be set longer
  • Just now I try to add delay time(10us) between read/write access , the continuous GPMC read/write result will be better, but still show dozens of errors