Tool/software: Linux
Hi all:
In my design, AM335x's GPMC indirecty connected to a SRAM with the help of a MVB device, the MVB device can receive the CS, WR, RD signal from GPMC bus, and then decide to send the CS, WR, RD signal to SRAM.
I config the GPMC to be non-multiplexed attached device connected, 16 bit, use wait1 input pin, read/write asynchronous, and set the timings as long as possible because the connect is indirectly, we must slow the speed.
After all below action, I can read and write the SRAM by single, also get the right timing sequence by oscilloscope, and get the right address line value and data line value , BUT!!!!!!!
If I act a cover test to the SRAM, such as write 0xFFF to all the address of the SRAM, and then read them all, Always I cannot get the desired result, sometimes I found the read value is wrong but when I read the same address manually, I found the return read value is RIGHT!
At first, I guess the interval between read/wirte access is to short, then I set the register CYCLE2CYCLEDELAY to 15, and enable CYCLE2CYCLEDIFFCSEN and CYCLE2CYCLESAMECSEN, but the modify action seems useless, I can found the read/write period is up to 2us which is long enough, but still get the same result, I have been trapped in the problem for almost half a month , please help me!! Thanks a lot!