AM5728: Mailbox interrupt to DSP fails

What software is this? Which version?

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Biser Gatchev-XID said:

What software is this? Which version?

Hello Biser,

I m writing a small bare-mental program. Here is my code:

/*
 * main.c
 */
#include "reg.h"

#pragma CODE_SECTION(main, ".text")
#pragma RETAIN(main)

int dsp1_intc_setup(void)
{
 unsigned int tmp = 0;

 // set the base address of vector table to 0x800000
 asm volatile(" MVKL 0x800000, B31 ");
 asm volatile(" MVKH 0x800000, B31 ");
 asm volatile(" MVC B31, ISTP ");

 // disable global interrupt
 asm volatile(" MVC CSR, B31 ");
 asm volatile(" AND 0xFFFFFFFE , B31, B31 ");
 asm volatile(" MVC B31, CSR ");

 // disable individual interrupt
 asm volatile(" MVK 0x0, B31 ");
 asm volatile(" MVC B31, IER ");

         // map the IRQXBAR event 52 (mailbox0_user0) to DSP IRQ4
 tmp = *INTERRUPT_MUX_1;
 tmp &= 0xFFFFFF00;
 tmp |= 0x00000034;
 *INTERRUPT_MUX_1 = tmp;

  // clear event flag register
 *EVENT_CLEAR_0 = 0xFFFFFFFF;
 *EVENT_CLEAR_1 = 0xFFFFFFFF;
 *EVENT_CLEAR_2 = 0xFFFFFFFF;
 *EVENT_CLEAR_3 = 0xFFFFFFFF;

 // clear all interrupt
 asm volatile(" MVKL 0xFFFFFFFF, B31 ");
 asm volatile(" MVKH 0xFFFFFFFF, B31 ");
 asm volatile(" MVC B31, ICR ");

 // enable DSP IRQ4, NMI and reset
 asm volatile(" MVK 0x13, B31 ");
 asm volatile(" MVC B31, IER ");

 // enable global interrupt
 asm volatile(" MVC CSR, B31 ");
 asm volatile(" OR 1, B31, B31 ");
 asm volatile(" MVC B31, CSR ");

 return 0;
}

int mailbox0_interrupt_setup(void)
{
 // disable all interrupt
 *MAILBOX_IRQENABLE_CLR_0 = 0xFFFFFFFF;

 // clear mailbox0 interrupt
 *MAILBOX_IRQSTATUS_CLR_0 = 0xFFFFFFFF;

 // enable NEWMSGENABLEUUMB interrupt only
 *MAILBOX_IRQENABLE_SET_0 = 0x05050505;

 return 0;
}

int main(void)
{
 unsigned int tmp = 0;
 unsigned int count = 0;
 unsigned int cmd = 0;

 dsp1_intc_setup();
 mailbox0_interrupt_setup();

 // endless while loop
 while (1) ;
}

interrupt void mailbox_isr(void)
{
 // read message
 *DUMMY_ADDR2 = *MAILBOX_MESSAGE_0;

 // clear IRQ by writing 1
 *MAILBOX_IRQSTATUS_CLR_0 |= 0x1;
}

/*
 * reg.h
 */

#define uint32_t unsigned int

/*
 * mailbox1's registers
 */
#pragma DATA_SECTION(MAILBOX_MESSAGE_0, ".data")
#pragma RETAIN(MAILBOX_MESSAGE_0)
volatile unsigned int *MAILBOX_MESSAGE_0 = (unsigned int *)(0x4A0F4040);

#pragma DATA_SECTION(MAILBOX_FIFOSTATUS_0, ".data")
#pragma RETAIN(MAILBOX_FIFOSTATUS_0)
volatile unsigned int *MAILBOX_FIFOSTATUS_0 = (unsigned int *)(0x4A0F4080);

#pragma DATA_SECTION(MAILBOX_MSGSTATUS_0, ".data")
#pragma RETAIN(MAILBOX_MSGSTATUS_0)
volatile unsigned int *MAILBOX_MSGSTATUS_0 = (unsigned int *)(0x4A0F40C0);

#pragma DATA_SECTION(MAILBOX_IRQSTATUS_RQW_0, ".data")
#pragma RETAIN(MAILBOX_IRQSTATUS_RQW_0)
volatile unsigned int *MAILBOX_IRQSTATUS_RQW_0 = (unsigned int *)(0x4A0F4100);

#pragma DATA_SECTION(MAILBOX_IRQSTATUS_CLR_0, ".data")
#pragma RETAIN(MAILBOX_IRQSTATUS_CLR_0)
volatile unsigned int *MAILBOX_IRQSTATUS_CLR_0 = (unsigned int *)(0x4A0F4104);

#pragma DATA_SECTION(MAILBOX_IRQENABLE_SET_0, ".data")
#pragma RETAIN(MAILBOX_IRQENABLE_SET_0)
volatile unsigned int *MAILBOX_IRQENABLE_SET_0 = (unsigned int *)(0x4A0F4108);

#pragma DATA_SECTION(MAILBOX_IRQENABLE_CLR_0, ".data")
#pragma RETAIN(MAILBOX_IRQENABLE_CLR_0)
volatile unsigned int *MAILBOX_IRQENABLE_CLR_0 = (unsigned int *)(0x4A0F410C);

/*
 * interrupt controller registers
 */
#pragma DATA_SECTION(INTERRUPT_MUX_1, ".data")
#pragma RETAIN(INTERRUPT_MUX_1)
volatile unsigned int *INTERRUPT_MUX_1 = (unsigned int *)(0x01800104);

#pragma DATA_SECTION(EVENT_CLEAR_0, ".data")
#pragma RETAIN(EVENT_CLEAR_0)
volatile unsigned int *EVENT_CLEAR_0 = (unsigned int *)(0x1800040);

#pragma DATA_SECTION(EVENT_CLEAR_1, ".data")
#pragma RETAIN(EVENT_CLEAR_1)
volatile unsigned int *EVENT_CLEAR_1 = (unsigned int *)(0x1800044);

#pragma DATA_SECTION(EVENT_CLEAR_2, ".data")
#pragma RETAIN(EVENT_CLEAR_2)
volatile unsigned int *EVENT_CLEAR_2 = (unsigned int *)(0x1800048);

#pragma DATA_SECTION(EVENT_CLEAR_3, ".data")
#pragma RETAIN(EVENT_CLEAR_3)
volatile unsigned int *EVENT_CLEAR_3 = (unsigned int *)(0x180004C);

/*
 * dummy address for debug purpose
 */
#pragma DATA_SECTION(DUMMY_ADDR, ".data")
#pragma RETAIN(DUMMY_ADDR)
volatile unsigned int *DUMMY_ADDR = (unsigned int *)(0x802000);

#pragma DATA_SECTION(DUMMY_ADDR2, ".data")
#pragma RETAIN(DUMMY_ADDR2)
volatile unsigned int *DUMMY_ADDR2 = (unsigned int *)(0x802004);

/*
 * reg.h
 */

#define uint32_t unsigned int

/*
 * mailbox1's registers
 */
#pragma DATA_SECTION(MAILBOX_MESSAGE_0, ".data")
#pragma RETAIN(MAILBOX_MESSAGE_0)
volatile unsigned int *MAILBOX_MESSAGE_0 = (unsigned int *)(0x4A0F4040);

#pragma DATA_SECTION(MAILBOX_FIFOSTATUS_0, ".data")
#pragma RETAIN(MAILBOX_FIFOSTATUS_0)
volatile unsigned int *MAILBOX_FIFOSTATUS_0 = (unsigned int *)(0x4A0F4080);

#pragma DATA_SECTION(MAILBOX_MSGSTATUS_0, ".data")
#pragma RETAIN(MAILBOX_MSGSTATUS_0)
volatile unsigned int *MAILBOX_MSGSTATUS_0 = (unsigned int *)(0x4A0F40C0);

#pragma DATA_SECTION(MAILBOX_IRQSTATUS_RQW_0, ".data")
#pragma RETAIN(MAILBOX_IRQSTATUS_RQW_0)
volatile unsigned int *MAILBOX_IRQSTATUS_RQW_0 = (unsigned int *)(0x4A0F4100);

#pragma DATA_SECTION(MAILBOX_IRQSTATUS_CLR_0, ".data")
#pragma RETAIN(MAILBOX_IRQSTATUS_CLR_0)
volatile unsigned int *MAILBOX_IRQSTATUS_CLR_0 = (unsigned int *)(0x4A0F4104);

#pragma DATA_SECTION(MAILBOX_IRQENABLE_SET_0, ".data")
#pragma RETAIN(MAILBOX_IRQENABLE_SET_0)
volatile unsigned int *MAILBOX_IRQENABLE_SET_0 = (unsigned int *)(0x4A0F4108);

#pragma DATA_SECTION(MAILBOX_IRQENABLE_CLR_0, ".data")
#pragma RETAIN(MAILBOX_IRQENABLE_CLR_0)
volatile unsigned int *MAILBOX_IRQENABLE_CLR_0 = (unsigned int *)(0x4A0F410C);

/*
 * interrupt controller registers
 */
#pragma DATA_SECTION(INTERRUPT_MUX_1, ".data")
#pragma RETAIN(INTERRUPT_MUX_1)
volatile unsigned int *INTERRUPT_MUX_1 = (unsigned int *)(0x01800104);

#pragma DATA_SECTION(EVENT_CLEAR_0, ".data")
#pragma RETAIN(EVENT_CLEAR_0)
volatile unsigned int *EVENT_CLEAR_0 = (unsigned int *)(0x1800040);

#pragma DATA_SECTION(EVENT_CLEAR_1, ".data")
#pragma RETAIN(EVENT_CLEAR_1)
volatile unsigned int *EVENT_CLEAR_1 = (unsigned int *)(0x1800044);

#pragma DATA_SECTION(EVENT_CLEAR_2, ".data")
#pragma RETAIN(EVENT_CLEAR_2)
volatile unsigned int *EVENT_CLEAR_2 = (unsigned int *)(0x1800048);

#pragma DATA_SECTION(EVENT_CLEAR_3, ".data")
#pragma RETAIN(EVENT_CLEAR_3)
volatile unsigned int *EVENT_CLEAR_3 = (unsigned int *)(0x180004C);

/*
 * dummy address for debug purpose
 */
#pragma DATA_SECTION(DUMMY_ADDR, ".data")
#pragma RETAIN(DUMMY_ADDR)
volatile unsigned int *DUMMY_ADDR = (unsigned int *)(0x802000);

#pragma DATA_SECTION(DUMMY_ADDR2, ".data")
#pragma RETAIN(DUMMY_ADDR2)
volatile unsigned int *DUMMY_ADDR2 = (unsigned int *)(0x802004);

Hi,

I am new to TI devices so I have no idea about CSL. But I would like to use CSL if it can reduce the development effort and communication time for us. 

I have some basic questions for you. Can you answer them?

1. Is CSL able be used without SYS/BIOS? If it is, how do we compile and link our program? Is there any other documentation besides the "Using CSL APIs Without DSP/BIOS ConfigTool" section of this documentation? 

 

2. Are there any documents for introducing CSL API for C6000? I have found this, but it doesn't mention UART and MAILBOX.

BR,

Hungwei

The CSL layer is register level and functional level APIs that directly interact with the MMR register on the SOC. functionally they are completely independent of any OS and is the TI recommended approach for bare-metal code development on TI Processors. 

Most of the documentation for CSL is linked from our software developers guide here:

http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_CSL#AM57x.2FK2x.2FC66x.2FC674x

The API guide for the CSL layer is found inside the PDK component that is packaged with Processor SDK RTOS:

pdk_am57xx_1_0_xx/packages/ti/csl/docs/doxygen/html/index.html

Regards,

Rahul

Hello,

1. Can I compile and link my CSL program in CCS? It seems that I can compile and link my program with CSL in Windows command line. 

2. I don'st see introduction of API related mailbox in the page of pdk_am57xx_1_0_10/packages/ti/csl/docs/doxygen/html/group___c_s_l___m_a_i_l_b_o_x.html. Is the version of documentation out-of-date?

BR,

Hungwei

Hello,

Thanks for your information. I can compile CSL example successfully now.

I still have some question. Do you provide documentation for introducing APIs which used to manipulate Mailbox and Interrupt Mux registers?

I am reading ti/csl/docs/doxygen/html/group___c_s_l___a_r_c_h___c66_x___i_n_t_e_r_r_u_p_t.html and ti/csl/docs/doxygen/html/group___c_s_l___m_a_i_l_b_o_x.html, but it seems the introduction is not complete.

For example, the html page for Mailbox does not mention how to use API.

I have found the declarations of APIs in csl\src\ip\malibox\V0\malibox.h, but I am wondering do you have better, complete documentation. Then we can spend a little time for using CSL.

The mailbox CSL-FL documentation is located at this location. Some how it doesn`t seem to be linking to the top level documention.
pdk_am57xx_1_0_10/packages/ti/csl/docs/doxygen/html/mailbox_8h.html
pdk_am57xx_1_0_10/packages/ti/csl/docs/doxygen/html/mailbox_8c.html

The doxygen documentation is created from the developer inserted comments so let us know if you find anything missing and we can provide more guidance.

Regards,
Rahul

Hello,

>Some how it doesn`t seem to be linking to the top level documention. 

That's how I feel...I cannot find the functions I want quickly and directly from the ti/csl/docs/doxygen/html/index.html. 

>if you find anything missing and we can provide more guidance.

Yes. I am looking any functions which are used to control interrupt selector to map one of 128 interrupt events to one of DSPINT4 ~ 15. Could you help me?

Thanks,

Hungwei

Hello Rahul,

I have traced ti\csl\arch\c66x\src\interrupt.c and rewritten my program with CSL library. After I push data into the message queue0 of mailbox1. The event2 and event52 has been raised which is shown as the following figure, but IER[5].IE05 still remains 0. It seems that the interrupt still doesn't work. Please give some comments. 

Thanks,

Hungwei 

#define MAILBOX_USERRR 0
#define MAILBOX_IRQ_NO 52
void mailboxisr(void *handle);
volatile unsigned int *DUMMY_ADDR = (unsigned int *)(0x802000);

int main(void)
{
	unsigned int i = 0;

    /*Pad configuration and PRCM enable*/
	//padConfig_prcmEnable();

    //UARTConfigPuts(uartBaseAddr,"\nSender: Mailbox Application ", -1);

    //UARTConfigPuts(uartBaseAddr,"\nSender: Send Message", -1);


    Intc_Init();
    Intc_IntEnable(0);
    Intc_IntRegister(MAILBOX_IRQ_NO, (IntrFuncPtr) mailboxisr, NULL);
    Intc_SystemEnable(MAILBOX_IRQ_NO);

    MailboxDisableQueueNotFullInt(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR,
                                MAILBOX_QUEUE_0);

    MailboxEnableNewMsgInt(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR,
    		MAILBOX_QUEUE_0);

    while(1)
    {
    	*DUMMY_ADDR = 0x77880000 + ((i++) & 0xFFFF) ;
    }

    //MailboxSendMessage(MAILBOX_BASE_ADDRESS, MAILBOX_QUEUE_0,
    //                    (uint32_t) MAILBOX_APP_MSG_TO_SEND);
}

void mailboxisr(void *handle)
{
    //gMsgStatus = MailboxGetMessage(MAILBOX_BASE_ADDRESS, MAILBOX_QUEUE_0, (uint32_t *) &gMsg);

    /* clear mlb intr */
    MailboxClrNewMsgStatus(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR, MAILBOX_QUEUE_0);

    //UARTConfigPuts(uartBaseAddr,"\nSender: receive Message", -1);

    *(DUMMY_ADDR+1) = 0xc4c4c4c4;
}

Hello,

Thanks for your help. Now the C66x can receive interrupts from USER0 of Mailbox1. But I still have one question for you.

From the TRM 17.3.2, MAILBOX1_IRQ_USER0 is mapped to DSP1_IRQ_52 after hardware reset. However, I need to add CSL_xbarIrqConfigure(...) to map DSP1_IRQ_52 to MAILBOX1_IRQ_USER0. Otherwise, the C66x will not process interrupt. Could you give some comment?

CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, gXbarInst , CSL_XBAR_MAILBOX1_IRQ_USER0); 

Best Regards,

Hungwei

int32_t intrC66x[] = {32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
                        43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
                        54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
                        65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
                        76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86,
                        87, 88, 89, 90, 91, 92, 93, 94, 95};

#define MAILBOX_USERRR 0
void mailboxisr(void *handle);
volatile unsigned int *DUMMY_ADDR = (unsigned int *)(0x802000);
unsigned int gXbarInst = 21;

int main(void)
{
	unsigned int i = 0;

    /*Pad configuration and PRCM enable*/
	//padConfig_prcmEnable();

    UARTConfigPuts(uartBaseAddr,"\nSender: Mailbox Application ", -1);
    UARTConfigPuts(uartBaseAddr,"\nSender: Send Message\n", -1);

	CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, gXbarInst , CSL_XBAR_MAILBOX1_IRQ_USER0);

    Intc_Init();
    Intc_IntEnable(0);
    Intc_IntRegister(intrC66x[gXbarInst-1], (IntrFuncPtr) mailboxisr, NULL);
    Intc_SystemEnable(intrC66x[gXbarInst-1]);

    MailboxDisableQueueNotFullInt(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR, MAILBOX_QUEUE_0);

    MailboxEnableNewMsgInt(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR, MAILBOX_QUEUE_0);

    while(1)
    {
    	*DUMMY_ADDR = 0x77880000 + ((i++) & 0xFFFF) ;
    }
}

void mailboxisr(void *handle)
{
	int i = 0;
	int count = 0;
    int gMsgStatus = 0;
    int gMsg = 0;

    MailboxDisableNewMsgInt(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR, MAILBOX_QUEUE_0);
    MailboxClrNewMsgStatus(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR, MAILBOX_QUEUE_0);

    count = MailboxGetMessageCount(MAILBOX_BASE_ADDRESS, MAILBOX_QUEUE_0);

    for (i = 0; i < count; i++) {
    	gMsgStatus = MailboxGetMessage(MAILBOX_BASE_ADDRESS, MAILBOX_QUEUE_0, (uint32_t *) &gMsg);
    	if (gMsgStatus == MESSAGE_VALID) {
    		UARTConfigPuts(uartBaseAddr,"Sender: receive Message ", -1);
    		UARTConfigPutHexNum(uartBaseAddr,(int32_t)gMsg);
    		UARTConfigPuts(uartBaseAddr,"\n", -1);
    	}
    }


    MailboxEnableNewMsgInt(MAILBOX_BASE_ADDRESS, MAILBOX_USERRR, MAILBOX_QUEUE_0);
}