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Linux/AM3352: DDR3 JEDEC spec violation in DS0

Part Number: AM3352

Tool/software: Linux

HI All,

I am using Linux 4.9.69 from latest TI official release on Am3352 (custom board). We are using DDR3 with 400MHZ.

Question is on JDEC compliance:

JDEC mandates 500us delay b/w DDR_RESET to DDR_CKE transition, which need to be configured in SDRAM_REF_CTRL register for this platform.
MLO seems to have configured it correctly to  500us (0x3100) initially and reset it back to 128us (0xC30)for normal operation.
So, later point of time (entire ON session) it is not changed and stays at 128us. 

This appears to be violation of JDED spec for low power use cases. Low power cases in which  DDR3  is put into self refresh (EMIF controlling CKE here) and when trying to bring DDR3 back to active, CKE may go high within 128us (based on SDRAM_REF_CTRL reg). 
Is that okay? 

This appears to me that, SDRAM_REF_CTRL should be changed to 0x31000 before entering SR and changed back to 0xC30 after CKE is enabled. 

Please let me know. 

Thanks