TAS2505: How to use software to enable TAS2505 to enter shutdown mode?

Part Number: TAS2505

dear all:

          How to use software to enable TAS2505 to enter shutdown mode? Which registers  need to configure? and What needs to be done to quit shutdowm mode?

thanks!

14 Replies

  • Hi David,

    Do you want a shutdown mode that does not require a reset to come out of shutdown?
    If you can toggle RST pin, I would suggest to pull RST pin down so that the device is back to default state, this would take the device into a minimum power consumption. To take the device back to operation you would follow the same initialization procedure.
    I you want a short time from shutdown to operation mode, you can power down as many blocks as possible, like PLL, DAC, output drivers (speaker, headphone), master reference, level shifters.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    dear ivan:

                pull RST pin down, The power consumption is relatively large . Can you provided DEMO code to Enabling and exit shutdown modes?

    thanks!

  • In reply to DAVID CUI:

    David,

    Do you have already an initialization script? I could use it as start-point to know what configuration you would need for the device to exit out of shutdown.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    dear ivan:
               This is my initialization configuration
    static const unsigned char Init_Table[] =              // Table of data to transmit
    {
      /// A2DP Sink - Enable Speaker Playback Class-D ///
      ///////////////// Initialization //////////////////
      // Px, P0              Switch to Page 0
      0x00, 0x00,
      // Software Reset Register
      // P0, R1, b0.         Reset = SW Reset - Internal Registers
      0x01, 0x01,
      // Px, P1              Switch to Page 1
      0x00, 0x01,
      // LDO Control Register
      // P1, R2, b5-4.       AVDD LDO Output = 1.8V
      // P1, R2, b3.         PLL and HP Level Shifters = Power Up
      0x02, 0x04,

      ////////////// Digital Configuration //////////////
      // Px, P0              Switch to Page 0
      0x00, 0x00,
      // Clock Setting Register 1 - Multiplexers
      //    -> PLL_CLK = (PLL_CLKIN x R x J.D)/P
      //    -> 84.672MHz = (3.528MHz  x 1 x 24.0)/1 --> For Fs = 44.1KHz
      //    -> XX.XXXMHz = (XXXXMHz  x X x XX.0)/1 --> For Fs = 48KHz
      // P0, R4, b3-2.       PLL_CLKIN = BCLK (01)
      // P0, R4, b1-0.       CODEC_CLKIN = PLL_CLK (11)
      0x04, 0x07,
      // Clock Setting Register 2 - PLL P and R Values
      // P0, R5, b7.         PLL = Power Up (1)
      // P0, R5, b6-4.       PLL Divider P = 1
      // P0, R5, b3-0.       PLL Divider R = 1
      0x05, 0x98,
      // Clock Setting Register 3 - PLL J Value
      // P0, R6, b5-0.       PLL Divider J = 24
      0x06, 0x18,
      // Clock Setting Register 4 - PLL D Value
      // P0, R7, b5-0. (MSB) PLL Divider D = 0
      // P0, R8, b7-0. (LSB)
      0x07, 0x00,
      0x08, 0x00,
      // Clock Setting Register 11 - NDAC Values
      // P0, R11, b7.        NDAC = Power Up
      // P0, R11, b6-0.      NDAC = 3 (DAC_CLK = CODEC_CLKIN / NDAC)
      0x0B, 0x86,
      // Clock Setting Register 12 - MDAC Values
      // P0, R12, b7.        MDAC = Power Up
      // P0, R12, b6-0.      MDAC = 8 (DAC_MOD_CLK = DAC_CLK / MDAC)
      0x0C, 0x88,
      // DAC Setting Register 1-2 - DOSR Value
      //     -> DAC_Fs = CODEC_CLK_IN / (NDAC.MDAC.DOSR)
      //     -> 44.1KHz = 84.672MHz / (3.8.80)
      //     -> 48KHz = TBD KHz / (X.X.80) TBD
      //     -> DOSR MUST be a multiple of 8 - slaa404c.pdf
      //     -> MDAC * DOSR >= ResourceClass * 32
      //     -> DOSR = 64, for Low-Power Mode
      //     -> DOSR = 128, for High-Performance Mode
      // P0, R13, b1-0.(MSB) DOSR = 80 (DAC_Fs = DAC_MOD_CLK / DOSR)
      // P0, R14, b7-0.(LSB)
      0x0D, 0x00,
      0x0E, 0x80,
      // Audio Interface Setting Register 1 - Configuration
      // P0, R27, b7-6.      Interface Mode = I2S Mode (00)
      // P0, R27, b5-4.      Data Length = 16bits (00)
      // P0, R27, b3.        BCLK = Input (0)
      // P0, R27, b2.        WCLK = Input (0)
      0x1B, 0x00,
      // Audio Interface Setting Register 2 - Data Offset
      // P0, R28, b7-0.      Data Offset = 1
      0x1C, 0x00,
      // DAC Instruction Set
      // Filter A - Best Performance, PRB_P1
      // P0, R60, b4-0.     Processing Block: PRB_P1
      0x3c, 0x01,
     
      ////////////// Analog Configuration //////////////
      // Px, P1              Switch to Page 1
      0x00, 0x01,
      // REF, POR and LDO BGAP Control Register
      // P1, R1, b4.         Master Reference = Power Up
      // P1, R1, b3.         POR Power Control = Power Up
      // P1, R1, b1.         LDO Bandgap = Power Up
      0x01, 0x10,
      // Common Mode Control Register
      // P1, R10, b6.        Analog Output Common Mode = 0.9V
      0x0A, 0x00,
      // P1, R3, b5.         DAC Mode = Enabled/Low-Power
      // P1, R3, b4-2.       DAC PTM Control = PTM_P3
      0x03, 0x00,
      };
  • In reply to DAVID CUI:

    Hi David,

    On the script I didn't found mention to any output driver, so I disabled both drivers in the script below. This script can be used to enter into shutdown mode.
    To exit out of shutdown mode you can power up each block in the reverse order, or you can also toggle the Reset pin and send the initialization script again.

    #############
    w 30 00 01
    # Mute HP
    w 30 10 40
    # Mute SPK driver
    w 30 30 00
    # Turn off HP
    w 30 09 00
    # Turn off SPK driver
    w 30 2D 00

    w 30 00 00
    # Mute DAC
    w 30 40 0C
    # Turn off DAC
    w 30 3F 36
    # Check for DAC to power down
    f 30 25 0xxxxxxx
    # Turn off MDAC
    w 30 0C 00
    # Turn off NDAC
    w 30 0B 00

    w 30 00 01
    # Turn off PLL & HP Level shifters
    w 30 02 04
    # Turn Off LDO bandgap, POR and Master Reference
    w 30 01 0A
    #############

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    Hi Ivan,

    Customer had programmed according your reply.

    They find VDD_SPK has below current waveform:

    Y-Scal 50uA/div, min value:20.4uA, max value:107uA, average value:33.2uA

    1. Why does this happen?

    2. But they find LDO output is 0.5V. Is this right?( I had asked this question in https://e2e.ti.com/support/audio/f/6/p/732872/2705747#2705747)

    Appreciate it for your help!

    Best Regards,

    Rock Su

  • In reply to Rock Su:

    Hi Rock,

    Is LDO being used in their application? What is LDO_SEL pin connection?
    I'll verify the script and SPKVDD behavior on my side.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    Hi Ivan,
    Customer connects LDO_SEL to VDD_SPK
  • In reply to Rock Su:

    Rock,

    I have tried the scrip on an evaluation board and the LDO output is off (GND).
    I'm working on the peaks observed on SPKVDD.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    Hi Ivan,

    Thanks a lot!

    Looking forward to your result.

    Best regards,

    Rock Su