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TLV320AIC24K: TLV320AIC24KIPFBG4 I2C interface

Part Number: TLV320AIC24K

Hi there,

With regards to the TLV320AIC24KIPFBG4 we have two questions with regards to the I2C interface.

  1. On the datasheet the Rise time (tr) of both SDA and SCL signals is specified as 300ns max. Since we are only operating at a SCL clock frequency of 100KHz can the limit be increased to 1000ns? Note that the reason I am suggesting 1000ns is because many other I2C devices allow this for slower clock frequencies – for example see datasheet for TCA9539RTWR and TCA9555RTWR.

  2. Is there spike / glitch filtering / suppression on the SCL & SDA I2C inputs? Note that it has been observed that many other ICs have 50ns spike suppression on these inputs and the parameter is normally called “tsp”. Even the TLV320AIC23B (similar device from same family) has it. In addition, the TCA9539RTWR and TCA9555RTWR also have the spike suppression.

Look forward to you your reply.

Regards,

Matthew

  • Matthew,

    re1: The max rise time is typically related to the Max SCL frequency. with a lower SCL frequency the max rise time may increase. 1000 nsec for a 100khz clock seems acceptable.

    Re2. I will need to look into that. The AIC23B was designed by a different team on a different process so drawing a parallel is hard. I will check with one of the designers and get back to you. Because of the age of the device, it may take a few days.

    best regards,
    -Steve Wilson
  • In reply to Steve-Wilson:

    Matthew,

    I spoke with one of the designers for the AIC24k and he has said that this device does have 50nsec glitch filter/spike suppression.

    best regards,
    -Steve Wilson