Part Number: TAS5756M
GVDD_REG power supply specification is not described in datasheet.
Waveform for startup sequence is attached below;
・On startup to 10 sec: 5.4V output and the after is 6.8V output.
・After I2C communication(Reset), GVDD is dropped to 5.4V for 1 sec and after become 6.8V.
Please let me know about two points question below;
①Is above waveform correct operation?
②Please let me know timing for read Vspk_GAIN/FREQ's DC voltage.
In reply to Satoshi:
When the voltage on the SPK_GAIN/FREQ pin is latched, the GVDD voltage is around 7V.
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In reply to Andy Liu SH:
Sorry for my reply delay,
Customer had additional question,
How long is the timing delay for start up (power on) to read Vspk_GAIN/FREQ's DC voltage?
About after start up, customer case is at first GVDD: 5.4V on 10 second and after become 6.8V. (It is not continuous 6.8V)
They want to confirm read timing is really 6.8V or not (5.4V).
Hi Satoshi, As I mentioned before, the transition from 5.4V to 6.8V in your scope capture is because the I2S clocks in the customer systems are starting to run at that time. The gain and switching frequency settings latching will only happen after this transition, which means GVDD is 6.8V when latching occurs. Andy
In reply to nazim zmirli26:
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