Part Number: TAS5756M
GVDD_REG power supply specification is not described in datasheet.
Waveform for startup sequence is attached below;
・On startup to 10 sec: 5.4V output and the after is 6.8V output.
・After I2C communication(Reset), GVDD is dropped to 5.4V for 1 sec and after become 6.8V.
Please let me know about two points question below;
①Is above waveform correct operation?
②Please let me know timing for read Vspk_GAIN/FREQ's DC voltage.
In reply to Satoshi:
When the voltage on the SPK_GAIN/FREQ pin is latched, the GVDD voltage is around 7V.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Andy Liu SH:
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.