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TAS5756M: Question about GVDD_REG power supply

Guru 15020 points

Replies: 20

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Part Number: TAS5756M

GVDD_REG power supply specification is not described in datasheet.

Waveform for startup sequence is attached below;

・On startup to 10 sec: 5.4V output and the after is 6.8V output.

・After I2C communication(Reset), GVDD is dropped to 5.4V for 1 sec and after become 6.8V.

Please let me know about two points question below;

①Is above waveform correct operation?

②Please let me know timing for read Vspk_GAIN/FREQ's  DC voltage.

Best regards,

Satoshi

  • In reply to Satoshi:

    Hi Satoshi,

    When the voltage on the SPK_GAIN/FREQ pin is latched, the GVDD voltage is around 7V.

    Andy

  • Guru 15020 points

    In reply to Andy Liu SH:

    Andy-san

    Thank you for reply,

    About Table 15; When 26dBv and 8 × fsync, is GVDD voltage around 5.44V~6.6V?
    Addition, please let me know about response time for detect and latch the voltage.

    Best regards,
    Satoshi
  • Guru 15020 points

    In reply to Satoshi:

    Any update on this?
  • In reply to Satoshi:

    Hi Satoshi,

    No. The voltage presented on the SPK_GAIN/FREQ pin is digitized and then decoded into a 3-bit word which is interpreted inside the TAS5756M device to correspond to a given gain and switching frequency.
    The 5.44V to 6.6V voltage range is the one corresponding to 26dBV and 8 × fsync.

    Andy
  • Guru 15020 points

    In reply to Andy Liu SH:

    Andy-san

    Sorry for my reply delay,

    Customer had additional  question, 

    How long is the timing delay for start up (power on) to read Vspk_GAIN/FREQ's  DC voltage?

    About after start up, customer case is at first GVDD: 5.4V on 10 second and after become 6.8V. (It is not continuous 6.8V) 

    They want to confirm read timing is really 6.8V or not (5.4V). 

    Best regards,

    Satoshi

  • In reply to Satoshi:

    Hi Satoshi,

    As I mentioned before, the transition from 5.4V to 6.8V in your scope capture is because the I2S clocks in the customer systems are starting to run at that time. The gain and switching frequency settings latching will only happen after this transition, which means GVDD is 6.8V when latching occurs.


    Andy

  • In reply to Satoshi:

    The constant power yield of any speaker is controlled by the warm execution of the enhancer just as constraints set on it by the framework around it, for example, the PCB arrangement and the encompassing working temperature.
  • Guru 15020 points

    In reply to nazim zmirli26:

    Thank you for reply,

    Sorry for additional question for timing diagram attached before;

    ①About Andy-san answered "run at that time", what is concrete signal?
     Is CLK/DATA input one-ckock correct?
    ②Is there timing specification and timing chart?
     Customer hope to confirm timing spec for GVDD start up, change to 5.4V~6.8V.
    ③About first GVDD change: 5.4V to 6.8V,
     What is trigger of change?
     Is trigger depend on time delay and this time is about 10 sec, correct?
    ④About second GVDD change: 6.8V to 5.4V to 6.8V,
     This recovery time: 1 sec is large differ from first change: 10 sec, why second GVDD change became fast?

    Best regards,
    Satoshi
  • In reply to Satoshi:

    Hi Satoshi,

    Can you post your new questions into a new thread? Thanks.

    Andy
  • Guru 15020 points

    In reply to Andy Liu SH:

    Andy-san

    I understood,
    I will make new thread near last question and modify customer information.

    Best regards,
    Satoshi

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