Part Number: SRC4192
I need to convert a 3 wire I2S input with possible sample rates of 44.1kS/s or 48/96/192 kS/s into a 4 wire I2S at a fixed sample rate (e.g. 48 ks/s) with added master clock (e.g. 24.576 MHz from a local oscillator). According to what I understand from the data sheet, SRC4192 should be able to do it with input port set as slave and output port set as master. I was just wondering whether having 44.1kS/s or 48/96/192 kS/s at the input could create any trouble (e.g. with internal buffering), since the said sample rates have no integer ratio... Would it be necessary to provide 2 different local oscillators depending on whether the input rate is 44.1kS/s or 48/96/192 kS/s (e.g. 22.5792 MHz or 24.576 MHz) and then switch between them ? In that case, how can the oscillator selection be automatically decided ? Or is the sample rate conversion anyhow correctly performed internally by just using a single local oscillator frequency ?
A second question is related to the input I2S data number of bits transmitted within a single LRCLK frame. In my system, in each LRCLK frame I have 32 data bits where the last 8 bits are 0. In other words, the 32 bit data word per channel frame is 0 padded in the last LSBs, so that in the end the real data bits are 24. I guess the SRC4192 can still handle this because I assume that as soon as the input serial buffer is full with 24 bit, more edges coming at BCKL should not produce any further bit shift in the input register. Or am I wrong ?
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