TLV320DAC3101: Continous noise with actual sound

Hi Khodidas,

The person in charge of this device is out of the office, so He will be responding tomorrow with further information.

Best Regards
José Luis Figueroa
Audio Applications Engineer

Hi Rutvik,

This is most likely a clock setting register issue. I'll closely review each line of the script but from a first glance I would recommend to set DOSR = 128 for best performance (that would modify the rest of the clock settings).
I'll provide further comments on the init script later today.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Rutvik,

I would recommend to use the following clock settings, if possible please try it and let us know if performance is improved:
PLL_P = 3
PLL_R = 4
PLL_J = 32
PLL_D = 0
NDAC = 3
MDAC = 29
DOSR = 128

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan,

We have tried your setting it improves sound but the noise is still there. Do you have any other suggestion in the above script.

Our requirement for the configuration is : 8KHz 16 bit data , BCLK- 256KHz , MCLK - 2.088 MHz.

We have also tried with the BCLK Configuration in DAC but still the noise is there.

For the BCLK We have changed the stated below things in the script. is it perfect? the sound behaviour of MCLK as CLK in and BCLK as CLK in is same.

/*CLK Gen using BCLK*/
DAC_Register_Write(0x04,0x01);

/*PLL Off*/
DAC_Register_Write(0x05,0x00);

/* NDAC = 1 MDAC = 1 DSOR = 32 */
DAC_Register_Write(0x0B,0x81);
DAC_Register_Write(0x0C,0x81);

DAC_Register_Write(0x0D,0x00);
DAC_Register_Write(0x0E,0x20);


Regards
Rutvik Fadia

Hi Rutvik,

Do you have captures of your I2S signals? I wonder if you would have to add a an offset on BCLK or even invert BCLK. Those are a couple things I would vary to see if there is any improvement.

About BCLK as input to PLL, I would not recommend this since BCLK is below 512kHz, which is the minimum input frequency for PLL.
I'll double check what else could be affecting audio from the device configuration you shared on the original post.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hello Ivan,

Please find the I2S wave form of

(1) WS(8KHZ) Vs BCLK (256KHZ)

(2) WS (8KHz) Vs DATA (16 bits)

Regards,

khodidas

Khodidas,

I've got a question from the captures above. Is the MSB of the Data valid on the first rising edge of BCLK or on the second one?
If data is valid on second rising edge of BCLK it would be I2S format, but if data is valid on the first rising edge of BCLK it would be Left-Justified format.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan,

We have verified our data we have problem in our data we have rectified it. Now our sound is clear . But we are getting another noise . I have added two audio recorded file if you hear you will get the idea what noise we are getting . One is when we transmit sound and another one is without the sound. Even If we turn off the I2S data sending and MCLK  from host controller then also this sound is coming out. 

Can you please share your view on this . Why this type of sound coming in the background.

Regards

Rutvik FadiaDAC_TEST_WITH_NOSOUND.aacDAC_TEST_WITH_SOUND.aac

Hi Rutvik,

Are you using the same configuration as before? Could you please send your init script or register dump just to confirm?
Is this noise like white noise in the background?
If you disable the I2S interface on the TLV320DAC3101 is the noise still present?

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi Ivan,

No we have modify the configuration as now our MCLK is precise 2.048 MHz . So we have changed according to that the register value. Rest of the thing is same. I have attached the new init script here.

For your second question yes the sound is like white noise in the background. This sound continously comes as soon as we start the I2S Communication from the host controller. If we disable the I2S and MCLK From the Host Controller then also this sound is not stopped .

For your Third Question we have not disable the I2S Interface on the DAC Side. We only turn it off and host controller side.

The Init Script is :

/*Page 0 */
DAC_Register_Write(0x00,0x00);

/*SW Reset Bit Clear*/
DAC_Register_Write(0x01,0x01);

/*PLL CLKIN*/
DAC_Register_Write(0x04,0x03);

/*Set PLL Power Down*/
/* J = 33 , D = 0 , P = 3 , R = 4 */
DAC_Register_Write(0x06,0x21);
DAC_Register_Write(0x07,0x00);
DAC_Register_Write(0x08,0x00);
/*Set PLL Power up*/
DAC_Register_Write(0x05,0xD4);


/*Set NDAC = 4*/
DAC_Register_Write(0x0B,0x84);

/*Set MDAC = 22*/
DAC_Register_Write(0x0C,0x96);

/*Set DOSR -> 128 Power Up with value 1*/
DAC_Register_Write(0x0D,0x00);
DAC_Register_Write(0x0E,0x80);


/*Set I2S Mode with 16 bit data*/
DAC_Register_Write(0x1B,0x00);

/*Set I2S Mode with 16 bit data*/
DAC_Register_Write(0x1C,0x00);

/*Set Processing Block PRB P11 */
DAC_Register_Write(0x3C,0x0B);

/*Set Page 8 For Adaptikve Filtering Enabled */
DAC_Register_Write(0x00,0x08);

/*Adaptikve Filtering Enabled */
DAC_Register_Write(0x01,0x04);

/*Set Page 0 For Volume initialization */
DAC_Register_Write(PG_CTRL0,0x00);

/*Volume control pin disable*/
DAC_Register_Write(0x74,0x00);

/*Set Page 1 For HP & SPK initialization */
DAC_Register_Write(0x00,0x01);


/*Set Common Mode Voltage to 1.35V */
DAC_Register_Write(0x1F,0x04);

/*De-pop, Power on = 800 ms, Step time = 4 ms*/
DAC_Register_Write(0x21,0x4E);

/*Set DACL->Routed to Left Channel and DACR-> Routed to Right Channel */
DAC_Register_Write(0x23,0x44);


/*Set Headphone gain */
DAC_Register_Write(0x28,0x06);
DAC_Register_Write(0x29,0x06);



/*Set Speaker gain */
DAC_Register_Write(0x2A,0x1C);
DAC_Register_Write(0x2B,0x1C);



/*Power up HPL and HPR */
DAC_Register_Write(0x1F,0xC6);



/*Power up Speaker */
DAC_Register_Write(0x20,0xC6);



/*Set Headphone Volume */
DAC_Register_Write(0x24,0x83);
DAC_Register_Write(0x25,0x83);



/*Set Speaker Volume */
DAC_Register_Write(0x26,0x80);
DAC_Register_Write(0x27,0x80);


/*Waiting Time*/
Delay(1000);

/*Set Page 0 DAC Power up */
DAC_Register_Write(0x00,0x00);


/*Power Up DAC for Left and Right Channels */
DAC_Register_Write(0x3F,0xD4);

/*Set Left Gain */
DAC_Register_Write(0x41,0x00);

/*Set Right Gain to */
DAC_Register_Write(0x42,0x00);

/*Unmute the Digital Volume of the DAC*/
DAC_Register_Write(0x40,0x00);


Regards
Rutvik Fadia

Rutvik,

As MCLK is 2.048MHz, this is already a multiple of 8kHz so you can use a simple clock settings by not using the PLL.
I'll check the rest of the script you shared but for the meantime, could you try with the following clock settings?:

/*MCLK as input to CODEC_CLKIN*/
DAC_Register_Write(0x04,0x00);

/*Set PLL Power Down*/
DAC_Register_Write(0x05,0x00);


/*Set NDAC = 1*/
DAC_Register_Write(0x0B,0x81);

/*Set MDAC = 2*/
DAC_Register_Write(0x0C,0x82);

/*Set DOSR -> 128 Power Up with value 1*/
DAC_Register_Write(0x0D,0x00);
DAC_Register_Write(0x0E,0x80);

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Hi, Ivan

By not using PLL removes the white noise problem . Now only we have some minor noise at some point in sound. We have setted the Maximum
analog volume and maximum gain does it create any issue. ?

Regards
Rutvik