TLV320AIC3104-Q1: TLV320AIC3104-Q1

Sunil BK

Hi Team,

I am using the above part to check the Leakage current for the power supply pins (DRVDD, AVDD, IOVDD and DVDD), for AVDD pin reading higher current than expected for other pins currents are in the limits.

Below procedure fallowed to check the leakage current.

1. Power on the device (AVDD = DRVDD = IOVDD = 3.3V & DVDD = 1.8V).

2. Run "Reset pattern" ( Pattern includes setting the Reset pins "Low" for 650ns and setting Reset pin "High" for 650ns. and measure the current across the power supply pins.

3. After reset we could see measured current are within the limits.

4. Run "Power patten" , In Power pattern setting the below registers.

REGISTER ADDRESS	DATA
0000 0111(07)	0010 1010(2A)	1.fS(ref) = 48 kHz 2.ADC dual-rate mode is disabled 3.DAC dual-rate mode is enabled 4.Left-DAC data path plays left-channel input data 5.Right-DAC data path plays right-channel input data
0010 0101(37)	1100 0000(C0)	1.Left and right DAC is powered up 2.HPLCOM configured as differential of HPLOUT
0010 1001(41)	0101 0000(50)	1.Left-DAC output selects DAC_L3 path to left line output driver 2.Right-DAC output selects DAC_R3 path to right line output driver 3.Left- and right-DAC channels have independent volume controls
0010 1011(43)	0000 0000(00)	1.The left-DAC channel is not muted 2.Left-DAC Digital Volume Control Setting is set to 0dB
0010 1100(42)	0000 0000 (00)	1.Output Driver Power-On Delay Control- Driver power-on time = 0 μs 2.Driver Ramp-Up Step Timing Control-Driver ramp-up step time = 0 ms
0101 0110(86)	0000 1001(09)	1.LEFT_LOP/M Output Level Control is set to 0dB 2.LEFT_LOP/M is not muted 3.All programmed gains to LEFT_LOP/M have been applied 4.LEFT_LOP/M is fully powered up
0101 1101(93)	0000 1001(09)	1.RIGHT_LOP/M Output Level Control is set to 0dB 2.RIGHT_LOP/M is not muted 3.All programmed gains to RIGHT_LOP/M have been applied 4.RIGHT_LOP/M is fully powered up

5. On writing the register 86 and 93 causing the high current drawn at "AVDD" pins, below attached PPT

PowerTest_TLV_3.pptx

6. Especially on writing bit 0 that is power on both Right and Left Lop causing the high current.

Let me know on your suggestions.

Thanks & Regards,

Sunil BK

over 5 years ago

0 Steve-Wilson over 5 years ago

TI__Mastermind 30030 points

Sunil,

Is your customer using an EVM? or is this their board? If customer board, would you be able to share a schematic? I can send you a connection request if they would rather share the schematic in private. I just want to make sure there is no issue with the output connections.

best regards,
-Steve Wilson

0 Sunil BK over 5 years ago in reply to Steve-Wilson

Prodigy 125 points

Hi Steve,

We are not using EVM, please find the attached schematic for your reference.

Thanks,

Sunil BK

0 Sunil BK over 5 years ago in reply to Sunil BK

Prodigy 125 points

Hi Steve,

Please let me know on the above query.

Thanks & Regards,

Sunil BK

0 Steve-Wilson over 5 years ago in reply to Sunil BK

TI__Mastermind 30030 points

Sunil,

can you give me a picture with higher resolution?
also, the schematic doesn't show where HPLOUT or HPROUT get terminated. Where do they go from there?

best regards,
-Steve Wilson

0 Sunil BK over 5 years ago in reply to Steve-Wilson

Prodigy 125 points

Hi Steve,

Please find the attached images for both Low power output and High power output schematic.

Low Power and High Power outputs are terminated at digitizer but there are 4 switches in the path from device output to digitizer.

let me know on your suggestions.

Thanks & Regards,

Sunil BK

0 Steve-Wilson over 5 years ago in reply to Sunil BK

TI__Mastermind 30030 points

Sunil,

Can you give more details about this Digitizer? what is the input impedance? is there a Coupling capacitor between the HP outputs and the inputs of the digitizer?

best regards,
-Steve Wilson

0 Sunil BK over 5 years ago in reply to Steve-Wilson

Prodigy 125 points

Hi Steve,

Q : Can you give more details about this Digitizer?

Ans: Sampling Rate: 32ksps to 200ksps, Resolution: 24bit, bandwidth: 50KHz, pin count: 4 single ended or 2 Differential, Input impedance: >1M in single ended or >2M in Differential, Filter: 50KHz (fixed anti aliasing), 6KHz and 30KHz digital filter. THD: -110dBc@ 1KHz, SNR : 125dBc @ 1KHz.

Q: Input impedance:

A: >Input impedance: >1M in single ended or >2M in Differential

Q: is there a Coupling capacitor between the HP outputs and the inputs of the digitizer?

A: No coupling capacitor between HP outputs and inputs of digitizer, but we have one 0 ohm in the path.

Thanks & Regards,

Sunil BK

0 Sunil BK over 5 years ago in reply to Sunil BK

Prodigy 125 points

Hi Steve,

Please find the attached PPT for the experiment detail done to find the behavior of the AVDD pin before and after reset pattern, help me in finding the cause for the higher leakage current.

Thanks & Regards,

Sunil BKPowerTest_TLV_1.pptx

0 Sunil BK over 5 years ago in reply to Sunil BK

Prodigy 125 points

Hi Steve,

I think i have sent all the details required, please let me know on your feedback on the above question. i am in critical need of it.

Thanks & Regards,

Sunil BK

0 Steve-Wilson over 5 years ago in reply to Sunil BK

TI__Mastermind 30030 points

Sunil,

I am surprised they are seeing such high current. is there any way to isolate the LEFT and Right LOP/M outputs? can we remove U13 and see how if the current changes?

best regards,
-Steve wilson

0 Steve-Wilson over 5 years ago in reply to Steve-Wilson

TI__Mastermind 30030 points

Sunil,

Were you able to remove U13 and see if the current changes?

best regards
-STeve Wilson

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TLV320AIC3104-Q1: TLV320AIC3104-Q1