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[FAQ] TAS Devices Information

TAS3108 Command Tool Software

/cfs-file/__key/communityserver-discussions-components-files/6/Command-Tool-Ver-6.02-_2800_USB-Version_2900_.zip

TAS3xxx Command Tool Software

Digital Audio Processor (DAP) Configuration Tool Operating Instructions

/cfs-file/__key/communityserver-discussions-components-files/6/DAS-DCT-_2800_USB-Version_2900_.zip

TAS5086 GUI 4.0

/cfs-file/__key/communityserver-discussions-components-files/6/TAS5086-GUI-4.0.zip

TAS50xx GUI 3.1

/cfs-file/__key/communityserver-discussions-components-files/6/TAS50xx-GUI-3.1.zip

TAS51xx Tips and Tricks

Q: TAS5103 PSRR

Are there any documents showing the difference between an open loop device PSRR and a closed loop device PSRR? For example TAS5103 vs TAS5706?

A: Re: TAS5103 PSRR

Hi,

I have attached a couple of files that will hopefully show the difference in PSRR between open loop and closed loop.

The file "PSRR Class D" is a document that specifically shows why PSRR in an open loop amp cannot be measured in the same way as a Class AB.

The file "PSRR.doc" has some plots of THD + N vs frequency of the TAS5103 with ripples at different frequencies. It also has the same plots for the TAS5706B (a closed loop device).

The file "slea049.pdf" is an app note that goes into detail on how ripple modulates with the switching frequency to create noise at the outputs.

/cfs-file/__key/communityserver-discussions-components-files/6/5751.PSRR.zip

Q: TAS5142, short circuit detection

Hi Team,

I would like clarification on the TAS5142 power stage short circuit detection. Is the short circuit detection monitoring for shorts between the differential outputs or between each output and PVDD/GND? Also, is there any other literature you can send me on how the fault is deemed short circuit as opposed to over current.


A: Re: TAS5142, short circuit detection 

Hi,

There is really no difference between a short circuit and over current protection in this family.

Yes, we can protect against overload conditions due to excess load current, shorts to ground, shorts to PVDD, AFTER the output filter.

TAS5342 actually has protection to find shorts upon power up, before the filter -- during manufacturing, sometimes there is a solder bridge between two pins. THe TAS53xx family can detect this and shut down prior to powering up. This prevents the chip from failing. The older parts, like TAS51xx family, will be destroyed under these conditions.

TAS53xx Tips and Tricks

Q: TAS5342 Question from Customer

Customer needs to have the TAS5342 part interfaced with a analog PWM - Is there an Analog PWM that can drive this part?


A: Re: TAS5342 Question from Customer

Hi,

The TAS3308 has analog inputs that go to an integrated ADC. An analog input Class D might be a better choice if there is no signal processing necessary.

The TAS5611 and TAS5613 are analog input class D amplifiers that fit into the 125-150W power range and support a 4 ohm load. Their high efficiency (>90%) and integrated closed loop feedback makes them a good choice in battery powered systems.

Figure 2 on page 12 of the TAS5613, and Figure 2 on page 13 of the TAS5611 datasheets show the output power that the amplifiers will produce at different voltage supplies.

Q: TAS5342LA vs TAS5342A

Please help me with the following questions?

1. What is (are) the primary difference(s) between the TAS5342LA and TAS5342A other than heat dissipation capabilities and voltage supply-to-gnd ranges for the bootstrap and half-bridge (output) sub-circuits?

2. Why was the TAS5342LA designed to have higher heat dissipation ratings vs. TAS5342A?

3. Why is the voltage supply -to- gnd voltage ranges lower in the TAS5342LA vs. the TAS5342 when both are rated for the same amount of output power? (For this question, I'm really trying to understand why the TAS5342A would allow for more output voltage swing of the output but dissipate less heat than the TAS5342LA.)

Help in understanding this device more throughly would be greatly appreciated!


A: Re: TAS5342LA vs TAS5342A

1) What are the primary differences?
TAS5342A has 80mR 50V Fets, TAS5342LA has 110mR 40V Fets
2) Why was the TAS5342LA/TAS5342L designed to have higher heat dissipation ratings than the TAS5342A?
The changes were made because it was cheaper for the customers. TI offers both the TAS5342A and
TAS5342LA so that the customer can choose if they want to pay for higher efficiency.

3) Why does TAS5342A allow for more output voltage swing but dissipate less heat than the TAS5342LA?
The abs max voltages are different because we used different FETs and different ESD cells to support these FETs.

TAS54xx Tips and Tricks

TAS5404-Q1

How do I request a TAS5404Q1EVM and install the App to control it?

Thank you for your interest in our products!

The below pdf shows how to request access to purchase the EVM, as well as requesting access to download the App to control it.

/cfs-file/__key/communityserver-discussions-components-files/6/TAS5404-EVM-and-PPC3-Instructions.pdf

TAS55xx Tips and Tricks

TAS5504 GUI 4.0

/cfs-file/__key/communityserver-discussions-components-files/6/TAS5504-GUI-4.0.zip

TAS5508 GUI 4.0

/cfs-file/__key/communityserver-discussions-components-files/6/0081.TAS5508-GUI-4.0.zip

TAS5518 GUI 4.0

/cfs-file/__key/communityserver-discussions-components-files/6/TAS5518-GUI-4.0.zip

TAS56xx Tips and Tricks

Clock for TAS5613

Generally the switching frequency for analog-input devices in TI's TAS56xx family (TAS5611TAS5613TAS5615TAS5630) is controlled by a single resistor.  It is also possible to use an external clock.

Each device includes a master clock oscillator, and its frequency can be trimmed with a resistor at the FREQ_ADJ pin.  The trim resistances and switching frequencies are shown under RECOMMENDED OPERATING CONDITIONS.  The master clock rate is 10 times the switching frequency.  To use an external clock, connect the FREQ_ADJ pin to VREG and drive OSC_IO+/- differentially with the external clock.

TAS5612PHD output voltage fluctuation

Q: TAS5612PHD output voltage fluctuation

A customer told us that they found TAS5612's output fluctuated when they changed PVDD in spite of TAS5612 'local feedback'.  All input signal conditions are 1kHz/20dB sine wave.

Could you let me know if it is a correct behavior?

A: RE: TAS5612PHD output voltage fluctuation

PWM devices like TAS5612 use feedback in the audio band to reduce distortion and output impedance and to improve PSRR, as specified in the data sheets.  However, there is power supply voltage feedback that is filtered to react only to changes near DC.  This makes it possible to use power supply volume control with these devices.  (Of course, this is possible with open loop power stages with PWM inputs.)

So TAS5612 will provide the performance shown in the data sheet, but it can also be used with power supply volume control.  That is what the customer sees.

Q: RE: TAS5612PHD output voltage fluctuation

I understand that the phenomenon customer found was PSVC behavior... am I correct?

If yes, then it is fully reasonable.

I will explain about the behavior.

A: RE: TAS5612PHD output voltage fluctuation

You are correct.  The behavior is PSVC.  (This means TAS5612 has no DC PSRR - however, its AC PSRR is still very good, because the local feedback applies in the AC range.)

 

TAS5614 EVM -PurePath Console connection

The TAS5614LADDVEVM is compatible with PurePath Console. However, some boards has an obsolete Firmware that is not compatible with this application.

In order to Use the TAS5614 EVM with PurePath Console, the firmware of the Input USB Board 3 must be updated. The required firmware files and instructions are included in the attached file. 

Also, the EVM must be populated with the TAS5558 to work correctly with Pure Path Console. Some boards has a TAS5538 on them, so this part must be removed and substituted with the TAS5558

/cfs-file/__key/communityserver-discussions-components-files/6/InpuUsb3Board_5F00_FirmwarePPC.zip

TAS5615 oscillation

LC filters for TI's class-D audio power amplifiers (APAs) are designed for very low losses, to maintain high efficiency.  This makes their Q's very high, so they can ring when the audio output of the APA includes significant transients, as in clipping or square-wave amplification.  

This ringing is not a form of oscillation, implying instability in the APA.  TI's APAs are designed for low output impedance and high stability regardless of load.

The ringing appears as a damped sinusoid at the characteristic frequency of the LC filter.  It begins at the onset and the end of clipping, where clipping creates sharp discontinuities in the audio output.  It also begins on the edge of any square wave transition or similar transient.  Generally it is not serious with a normal load.  These transients can be expected to generate higher ringing when there is no load.

TAS5615 Response Outside Audio Range

Q: TAS5615

Hello,

My input frequency can range from 5-50 kHz. I am curious as to what kind of attenuation I could expect from the TAS5615 from 20-50kHz.

Thanks.

A: Re: TAS5615

Hi,

The 5615 should be flat up to 80kHz input frequency. Obviously you might need to change the output filter a little bit, but the amplifier itself should work at 50kHz input perfectly fine.

TAS5616 in a noisy 12v environment

For high power in automotive applications with 8 and 4 ohm speakers, a boost converter can used with audio power amplifiers (APAs) like TAS5616 to provide the increased power supply voltage it requires.  The following are some notable issues in an application like this.

- Boost converter ripple must be controlled to prevent interference.  Ripple magnitude must be kept low enough to be rejected by APA PSRR, and it is generally best to syncronize the switching frequencies of the converter and the APA to integer multiples to avoid audible beats.

- Digital input transmission may be the best way to send inputs to the APA without interference. It is still vital to prevent clock or data corruption by other voltages in the system, because of the noise and distortion that may cause.

TAS5630 - Sonar Application - Driving a Transformer and Capacitive Load

Q: TAS5630 - Switching Frequency

1) What is the range of PWM switching frequencies that can be selected?  Specifically can the switching frequency increase above 400 kHz. 

2) How does the feedback loop work in this device?  Voltage-controlled? Current-controlled?

3)  How can the switching frequency be changed?  In the datasheet it lists two ways to adjust the frequency.

         a) FREQ_ADJ pin - trim the oscillator frequency, results in frequencies lower than 400 kHz.

          b) An external oscillator, is this the only way to get above 400kHz?

A: Re: TAS5630 - Switching Frequency 

1) The switching frequency range is 225k to 500kHz.

2)  The feedback is voltage controlled.

3)  You are correct, changing the FREQ_ADJ pin will only produce frequencies lower than 400k. An external oscillator will have to be used to achieve PWM frequencies of >400k. Also remember this oscillator must be 10xPWM frequency, so for a 400k PWM, the user must feed 4MHz.

TAS5630 AD or BD modulation

Q: TAS5630 AD or BD modulation

Hello,

I have a question about the AB or BD modulation to use the TAS5630 in btl configuration.

For my application i will use long cable between the amplifier and the speaker (about 5-10 meters)

What is the best for EMC consideration?

Thanks

A: Re: TAS5630 AD or BD modulation

Hello,

There shouldn't be that much a difference for well designed systems, but BD modulation will typically edge out AD in a general scenario due to slightly reduced transmission of switching frequency noise.

http://focus.ti.com/lit/an/sloa119a/sloa119a.pdf is a useful document that we have on our website to help design an LC filter for your application.

TAS5630, Short Circuit Protection

Q: TAS5630, Short Circuit Protection

Hi,

Could you please clarify on the short circuit protection in TAS5630DKD IC. I have been asked by the customer to short the output of this amplifier (that is, shorting the two leads of the differential output) for 24 hours and check whether the Amplifier IC is still alive.  Please advise whether this test can be done? Is there any short circuit protection provided in this IC?

A: Re: TAS5630, Short Circuit Protection

Hello,

The TAS5630 has a short circuit detection system for shorts between an OUT_X pin and either GND or PVDD. However, this system will not detect a short between two output pins, and it only works during startup. Please se page 23 of the TAS5630 datasheet for more information.

However, the Over current protection should detect if there is a problem at the outputs that could potentially damage the device. This will only happen if an audio signal is applied so that you are forcing two different voltages at the output, or if the switching frequencies of the two shorted outputs are out of phase. Either of these two scenarios will cause at least one channel to turn off in order to stop the high current.

Another thing to consider is the long speaker wires. If their resistance is large enough, a short might not be detected since the current will never reach the OCP threshold (and this is technically not a short since the amplifier does see some impedance in the output path). Either way the IC should protect itself if there is a large enough current that would damage it.

We have seen situations in which long speaker wires get hot when they are shorted because the amp sees a normal load and does not shut off. The solution to this is to make sure you are using thick enough wires that are rated for the desired max power.

TAS5630PHD2EVM Heatsink

The Heatsink that is listed in the TAS5630PHD2EVM Bill of Materials (TIC-HSINK-060(2.00)) is not available for purchase.

There is an alternative from Advanced Thermal Solutions Inc, the ATS-TI1OP-518-C1-R1 is designed for the TAS5613PHD2EVM and is compatible with the TAS5630PHD2EVM.

TAS57xx Tips and Tricks

I2S Clock Requirements on TAS570x/1x/2x/3x device's

 The TAS570x/1x/2x/3x devices are SLAVE-ONLY I2S devices that require all of the following clocks for audio play-back.

1.) MCLK  (Master Clock)

2.) SCLK  (Bit Clock)

3.) LRCLK (Frame Clock)

The devices have a built-in clock auto-detect monitor that continuously monitors the I2S clock rate's and ratio's [1*]. When valid clocks are provided, the device is in a "Lock-Mode" and can play audio (with a valid data-input signal & I2C register initialization).

In the event of non-valid clock rate's or ratio's being provided, the device enters "Limp-Mode" and can NOT play audio -- If the registers are initialized, the device PWM output signal will continue to switch in idle (50% duty-cycle). Further, a clock-error flag is set in the error-register. 

A distinguishing feature of the Limp-Mode from the Lock-mode is a lower PWM switching frequency. The typical lock-mode PWM switching rate on these devices is 384 kHz -- In Limp mode, the PWM frequency is less-than 340 kHz.

The clock-control register 0x00 (which is a read-only register) can be polled to check the clock rate's & ratio's detected by the auto-detect block. For example, a  read-back of x6C indicates LRCLK=48KHz, MCLK=256*Fs

The supported Clock rates for TAS5704/05/06/16 are the specified in the next table. 

For most others TAS57xx products, the clock rates are the specified next.

Notes:-

1.) For most TASS57xx devices, 44.1/48-kHz mode allows the use of a 64*Fs MCLK rate. This rate also happens to be one of the supported SCLK rates. In system's where only one clock may be available, a common MCLK=SCLK=64*Fs rate is an option to overcome the limitation. -- This is valid only if the Fs rate is 44.1/48-kHz.

2.) I2C read/write operations can be performed even without the clocks being provided.

3.) The Datasheet of these devices, describe how an internal clock (DCLK) is used in the absence of external MCLK. -- This internal clock (DCLK) is only used for sustaining the I2C & Idle-PWM switching activity. Without MCLK, the device will be in limp-mode & can NOT play audio.

[1*] After the Oscillator Trim register 0x1B is initialized by writing a value x00. (Note:- Default read-back of register 0x1B is x82 -- After initializing by writing x00, the read-back is xC0)

MC57xPSIA Board - input Configuration

Analog input (RIN/LIN)

  • Select ADC in JP4 and JP5 (short on pins 1 and 2).
  • Audio CLK jumpers (JP6-JP10) should be connected with pins 1 and 2 tied. 
  • JP2 and JP3 will limit the input voltage:
    • IN: LIN/RIN = 1Vrms MAX.
    • OUT: LIN/RIN = 2Vrms MAX. 


Digital input (Opto/RCA)

  • Select SPDIF in JP4 and JP5 (short on pins 2 and 3).
  • Audio CLK jumpers (JP6-JP10) should be connected with pins 1 and 2 tied. 
  • JP11 selects the SPDIF source:
    • Opto: pins 1 and 2
    • RCA: Pins 2 and 3


External PSIA input (I²S)

  • Connect the PSIA clock signals to pin 2 of Audio CLK jumpers (JP6-JP10).
  • Connect the PSIA GND to pin 3 of Audio CLK jumpers (JP6-JP10).

TAS5704 Clock error detection time

Q: TAS5704 Clock error detection time

Hi team,

- How many seconds does it take from the stop of the MCLK to the error detection?

- How about LRCLK and SCLK?

 
A: Re: TAS5704 Clock error detection time

Hello,

The chip detected a simple MCLK, LRCLK, or SCLK error in about 10us. Keep in mind that the important thing to remember here is that this is fast enough as to not allow any audio artiacts reverberate through the speakers. Essentially, you don't want the listener to be bombarded with noise while the chip recovers. Our responds plenty fast enough as to not allow this (10us -> 100kHz)

Also know that the time it takes the amplifier to recover also depends on what type of CLK error happened. Our 10us measurement is from a standard error, which would occur if a CLK signal was zeroed out.

TAS5704 DC/DC converter for AVDD and DVDD

Q: TAS5704 DC/DC converter for AVDD and DVDD

Hi team,

Our customer  wants to use 3.3V DC/DC converter for AVDD and DVDD of TAS5704. Is it OK? If it is OK, could you tell us the maximum ripple voltage of DC/DC converter?

A: Re: TAS5704 DC/DC converter for AVDD and DVDD

A DC/DC converter is fine. Our EVM's use a DC/DC to create the 3.3V for AVDD/DVDD.

The ripple on the AVDD should be below 80mV for best performance. I calculated this number with the PSRR of AVDD ( about 65dB) and the noise floor of the device. In other words I calculated the ripple on AVDD which would cause a signal at the output larger than the output noise (56uV from D/S).

The ripple can be larger, but audio performance will degrade. Of course, AVDD MUST remain over 3V in order for the amplifier to remain operational.

DVDD is more lenient and can handle more ripple, although it also should not fall below 3V.

TAS5706B PBTL

Q: TAS5706B PBTL

Hello,

Are there any I2C files for the TAS5706B used in PBTL mode?


A: Re: TAS5706B PBTL

Yes, Here are three files with two different PBTL modes and an extra BTL (different configuration than the one in the EVM user's guide.

/cfs-file/__key/communityserver-discussions-components-files/6/0724.I2C_5F00_Files.zip

TAS5706_BD_2p0ch_PBTL.ini  - First case, PBTL with A-D(L+) shorted and B-C(L-) shorted.

TAS5706_BD_2p0ch_BTL_CD_Inv.ini - Second case, BTL where A(L+) B(L-) C(R-), and D(R+).

TAS5706_BD_2p0ch_PBTL_v2.ini - Third case, PBTL with A-B(R+) shorted and C-D(R-) shorted.

TAS5707 and TAS5602 Idle current

Q: TAS5707 and TAS5602 Idle current by

 
Hello,

Could you let us know following data of TAS5707 and TAS5602;

-Quiescent supply current at 
Condition 1: Idle (no output), PVDD = 16V, RLoad = 4ohm 
Condition 1: Idle (no output), PVDD = 16V, RLoad = 8ohm


A: RE: TAS5707 and TAS5602 Idle current

Data measured on EVM:

For the TAS5707 I measured the following current coming from PVDD:

4 ohms: .117A

8 ohms: .116A

Note that this does not include the current going into DVDD which is about 48mA.

For the TAS5602,

4 ohms: .06A

8 ohms: .059A

In both devices, there is almost no change in currents because the output filters are able to block most of the switching frequencies. As Don mentioned earlier, a different filter might cause much higher currents.

TAS5707 Startup Sequence

Q: TAS5707

We would like to get the start up, normal operation and shutdown baseline register settings that we could use to bring the part up.


A: Re:  TAS5707

Here is the startup sequence for TAS5707:

/cfs-file/__key/communityserver-discussions-components-files/6/4747.TAS5707_5F00_BD_5F00_2xBTL_5F00_New.txt

TAS5707/09A I2C Address Setup

TAS5707A/09A is identical in function to TAS5707/09, but has a unique I2C device address. The address of the TAS5707/09 is 0x36. The address of the TAS5707A/09A is 0x3A. To configure the correct I2C address for these devices, it is needed to create or modify PPSI2C environment variable.

  1. Press Start, then right click on My Computer and select Properties as shown in Figure 8.

    Figure 8. Selecting My Computer Properties from Windows Start Menu

  2. At the system Window, click on Advanced system settings. Then, click on the Environment Variables button, as shown in figure 9.                         

    Figure 9. System properties, Advanced Tab and Environment Variables windows.

  3. In the User Variables section of the dialog, scroll through the list to see whether the variable PPSI2C shows. If the variable is not already listed, click the New button. If the variable name PPSI2C already exists in the list, click on PPSI2C to select it, and then click the Edit button. The Edit User Variable window appears, as shown in Figure 10.

    Figure 10. Edit User Variables Dialog.

  4. In the window shown in Figure 10, type PPSI2C as the variable name (for new variables). The variable value should be 3Afor TAS5707A/09A. Click OK and close the dialog boxes. Verify if correct I2C address is used by looking at the symbolization name printed on the device installed on the EVM being used, as shown in figure 11.

    Figure 11. TAS5707A installed on TAS5707EVM

TAS5708 into 4-ohm BTL

Q: TAS5708 into 4-ohm BTL 

I want to use 4ohm speaker with PVCC at 12V, so I think it should be ok for us except the thermal will be higher. Could you kindly help me confirm it?

Thanks.

A: Re: TAS5708 into 4-ohm BTL

Hello,

I tested this in the lab with Pvcc = 12 V and stereo 4R loads in BTL.

I ran it at 15W for 1.5 minutes with no change in output power or THD. I then ran it at 20W per channel for 15 mins without thermal shutdown and no runaway. The THD was at 13.5% for test, so as long as you stay under 10% THD, you're not thermally limited because of the low Pvcc.

TAS5709 document to calculate the loop filter values

Q: TAS5709 document to calculate the loop filter values

I am looking in to implementing a TAS5709 in a stereo I am designing. It looks really good except the data sheet refers to a document to calculate the loop filter values that I can’t seem to find. Do you know where I can find the TAS5709 User’s Guide for loop filter values? The EVM User’s guide didn’t have any information about it.

A: TAS5709 document to calculate the loop filter values

Sorry this is a little confusing. The EVM Users Guide can be found here, and the loop filter consists of C9, 10, 11, 13, and R5 and R8. These values should be used exactly.

TAS5711/27/31 Configuration on PBTL Mode.

TAS5711/27/31 are devices capable of drive a PBTL in single filter mode. They have a special pin that configures the device internally for working in this mode.

When PBTL  pin is pulled high, the device’s power stage bridges internally the outputs A with B and C with D.

However, what output is used for each bridge its determined by the device’s Power die. The other output of the bridge is ignored.

TAS5711 has a different power die than TAS5727/31, so in order to find for each device which is the used outputs, a simple test was made.

With the devices configured in PBTL mode and only changing the value of  PWM OUTPUT MUX and PWM SHUTDOWN GROUP registers, a small table was filled considering if the device’s output is working or not.

*PWM’s number in brackets correspond to the number assigned in Output register for each PWM.

 As can be seen, the device only works when the enabled PWM channels are selected for outputs B and D, while outputs A and C are ignored.

 

*PWM’s number in brackets correspond to the number assigned in Output register for each PWM.

 As can be seen, the device only works when the enabled PWM channels are selected for outputs A and C, while outputs B and D are ignored.

Then, as conclusion we have that:

For TAS5711:

The used outputs are B and D, therefore, A and C are ignored.

In PBTL mode, PWM OUTPUT MUX (0x25) Register's value should be:

 0x 01 10 32  45 IF  PWM SHUTDOWN GROUP (0x19) register's value is 0x3A. 
 0x 01 01 23  45 IF  PWM SHUTDOWN GROUP (0x19) register's value is 0x35. 

 

For TAS5727/31:

The used outputs are A and C, therefore, B and D are ignored.

In PBTL mode, PWM OUTPUT MUX (0x25) Register's value should be:

 0x 01 01 23  45 IF  PWM SHUTDOWN GROUP (0x19) register's value is 0x3A. 
 0x 01 10 32  45 IF  PWM SHUTDOWN GROUP (0x19) register's value is 0x35.

TAS5713 EVM Questions

Q: TAS5713

My customer would like to acquire 2 TAS5713PHP kits for development purposes.  After reviewing the information in the users guide (SLOU281), it was not clear if the eval kit included the MC57xxPSIA controller board along with the TAS5713 EVM.  Is it?

Also, is the MC57xxPSIA interchangable between the TAS 5713, 5715 and 5727 amplifiers or are the xx designators specific to each?

Thanks


A: Re: TAS5713PHP

There was recently a mix-up with the TAS5713 EVMs, some were shipped without the MC57xx-PSIA board, but this was a mistake by our vendor. If you or your customer needs one, please let us know.

A: Re: TAS5713PHP 

The MC57xx PSIA can be used with all TAS57xx devices, including the TAS5713/15/27.

TAS5717 - DC Detection

Q: TAS5717 - DC Detection.

Sir,

As I remember TAS5717 with DC detection, am I right? If yes, pls provide detail DC protection data to us due to I cannot get ant information in d/s. 

Q: Re: TAS5717 - DC Detection.

Hello
Yes, that is exactly what it will detect:  stuck (high or low) PWM.  As I mentioned, we send it constant value (DC) to SDIN then read register 0x02 bit 0.  Customer can do the same with DC component in SDIN data.

Q: Re: TAS5717 - DC Detection. 

Hello

Please let me clarify for you register 0x03 and 0x46 functions.

0x03 : 1st order HPF with Fc at 1Hz, automatically block DC components in the data stream - no users' interactions.

0x46:  PWM maximum duty cycle detection.  Needs external MCU to poll 0x02 bit 0 for error and then MCU needs to reset or shutdown system when error occurs.

You can test 0x03 using the AP with SPECIAL digital output signal.  Turn HPF on and do a frequency sweep, then measure again with HPF turned off.

You can also test 0x46 the same way - be sure to turn off HPF 0x03. Then use SPECIAL digital output signal from the AP and then read the 0x02 bit 0 for error.  Make sure no loads or speakers are attached.

Here's the AP SPECIAL digital signal setup.

Q: Re: TAS5717 - DC Detection. 

Sir,

As mention 0x46 bit 10 can enable DC bllocking, but how about 0x03 bit7? It also describe enable DC blocking, what different betwen 0x03 and 0x46?

Q: Re: TAS5717 - DC Detection. 

The DC blocking filter is after all other audio processing blocks to prevent DC from all potential sources.

Like he mentioned, It is a a first-order, digital, high-pass filter The filter –3-dB point is approximately 1Hz.

I suggest, tell your customer that we have DC blocking filter after DAP (digital audio processor) and give the paramters. DC filter sits just before PWM block.

TAS5717 HP EQ

Q: TAS5717 HP EQ

Pls help for 2 questions about TAS5717 HP,

1. D/S shows HP function register is 0x05=13, it'll serious noise if I writing 1B (volume in headphone mode =0x08/0x09 (same as speaker channel volume)). Could you pls check it?

2. I can using 0x26(bq(0)) to change HP EQ and work good but cannot get correct response if using 0x27(bq(1)), 0x28(bq(2))... 

A: Re: TAS5717 HP EQ

Here's the summary:-

Issue 1.) High Noise reported on HP outputs, when register 0x05 is selected to set channel-volume registers to control HP-volume.

Debug Notes: As I mentioned in the earlier post, I found that toggling this bit also changes the PWM modulation mode from AD to Ternary. The data-sheet needs to be updated to remove this as an option (and only allow HP volume control)

Work-Around: As of now, the only option is to use HP-volume control register to update the HP volume.

 

Issue 2.) HP-EQ doesnt seem to be working (only 1st bi-quad works) all others have no effect.

Debug Notes: Register 0x50 bit '6' controls the HP-EQ enable/by-pass mode.

Resolution: Datasheet indicates this bit as reserved. This will be updated shortly. To Enable HP-EQ, please change Bit-6 status & also set bit '7' to by-pass speaker EQ mode.

 

Also, for issue-1, it might be worth trying the following experiment to see if any improvement can be made on the noise-issue. In HP mode, after toggling the bit status to channel-volume control (i.e. where the noise  issue is seen), please use register 0x20 to [00-89-77-72] to set device in BD mode.

 

Q: Re: TAS5717 HP EQ

Thanks for your great information.

I write 0x50 to 0F-70-80-40(Defult: 0F-70-80-10) and HP can using EQ.

But I found GUI has issues, I need to fill up EQ setting then write 0x50-it'll success.

If I write 0x50 first, last byte 40 will be chenged to default 10 when I fill up EQ then push "APPLY & DRAW" bottom-EQ cannot be load to HP.

TAS5717 info

Q: TAS5717 Info

 

A: TAS5717

In the HP not-used case,  HPVSS should be tied to GND, this can of-course be done through a 0R. But in the case where HP is being used, the resistor should be replaced with a cap (as shown in EVM schematic). 

The filter-topology used on the EVM is a 2nd order low-pass filter in MFB (Multi Feed-Back loop) configuration. An excellent resource that describes this in detail is the following TI app-note: http://www.ti.com/lit/an/sloa049b/sloa049b.pdf

 

A: TAS5717

>> Needed >>

 

1.) Tie AVDD, DVDD to prevent any sequencing issues. 

2.) Tie HPVDD to 3.3V. (Although Headphone is not used, it is best to tie HPVDD to 3.3V, to prevent unintentional forward biasing internal diode structure). As long as HP-shut down is tied low, the HPVDD will draw negligble current.

3.) Resistor Osc_res should be low tolerance resistor. (1% or lower)


>> Optional >>

5.) Head-phone inputs & outputs can be tied to GND or left floating

6.) HPVSS can be tied directly to GND

7.) Cap C67 (between CPP & CPN) can be removed. CPP can either be floating or tied to 3.3V. CPN can either be floating or tied to GND.

8.) HP-shut down can be tied to GND directly

 

 Additional Information:

1.) Should I be pulling the headphone inputs low?    {{ Can be tied low or left floating }} 

2.) Is there anything wrong with not powering the HPVDD?   {{ Could cause forward-biasing internal diode structures. Best to tie to 3,3V, and keep HP-SD low}} 

3.) Or not connectng HPVSS low  {{ HPVSS should be tied to GND, for the same reason as point#2 above) }}

4.) Do you know how much power will be consumed when both (PDN & RESET) are low?  {{ Will be similar to the case where RESET is held low}}

5.)  Inductors at the output will be changed to something smaller than what they are now. {{Comment:-- This will result in higher idle current, i.e. larger power consumption in idle mode. Just wanted to point this out since power-consumption was indicated to be a key care about.)

6.) I can cut the power off during power-off mode if necessary (trying to meet under half watt), but I have space issues and I’m a bit worried about pop-noise if I cut power.  {{Comment:-- Power-Off will most likely result in an audible pop.}}

TAS5717 Lineout

Q: TAS5717

Sir,

Can I get 2.8Vrms on the LINEOUT or HP outputs?

A: Re: TAS5717

Hello,

It isn't possible to get 2.8Vrms out of either the HP or LINEOUT due to the fact that they're both running off of a 3.3V positive rail and -3.3V negative rail from the charge pump. The most you're going to be able to get is about 2.3Vrms.

TAS5717 Line-Out THD+N and SNR (I2S input)

When using the TAS5717 configured with an I2S digital audio input and Line-out, the THD+N of the device's output is represented in the next chart.

Figure 1. THD+N of TAS5717 Line out with I2S input. 

With this settings, SNR for this device is close to 81.8-dB.

Q: TAS5727 PBTL Register Settings 

 

I am looking that the datasheet for the TAS5727 and trying to figure out the configuration for PBTL mode.
 
Specifically, I am unsure how to program the input multiplexer register 0x20. We are driving only one speaker, so the digital signal for that will come in on SDIN-L. This currently gets routed to channel1, but from the PWW output mux register setting, it actually multiplexes channels 1 and 2. So do I need to route SDIN-L to both channel1 and channel2? Then, in reg19 we put channels 1 and *3* to not belong to a shutdown group. Where does channel 3 come from? For some reason the datasheet doesn’t really explain these channel mappings at all.
 
It gives some values to set  as follows:

 "PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should

be written with a value of 0x0110 3245. Also, the PWM shutdown register (0x19) should be written with a value"

 

Currently I have the following settings (not in the right order):

 reg 0x05 = 0x00 (Unmute all channels not in a shutdown group)

reg 0x07 = 0x00 0xd8 (Master volume = -3dB)

reg 0x19 = 0x3a (as recommended above, Channels 1 and 3 don’t belong to shutdown group)

reg 0x1b = 0x00 (Default trim)

reg 0x20 = 0x00 0x01 0x77 0x72 (SDIN-L to channel1, SDIN-R to channel2)

reg 0x25 = 0x01 0x10 0x32 0x45 (as recommended above, channel2 to OUT_A, channel1 to OUT_B, channel2 to OUT_C, channel1 to OUT_D)

A: Re: TAS5727 PBTL Register Settings 

Hi 

I know the confusion because I was in the same boat!  Here is the zip file that sets up the PBTL channel.  I checked this with the TAS5727 EVM.  The file names and comments are self-explanatory.  Please let me know otherwise.

/cfs-file/__key/communityserver-discussions-components-files/6/2318.TAS5727PBTL.zip

TAS5760 I2C address clarification

Question: 

For TAS5760, whether the I2C address is correct or not. We think the correct address should be  DA / D8  instead of 0x6C or 0x6D.

Answer:

It is not unreasonable for the hex value to be represented both ways. It is a little confusing, but I'll try to explain it below. (Please note that I am going to assume that the SPK_SLEEP/ADR Pin is pulled low for the examples below, to remove that variable and, hopefully, reduce confusion)

The full 8 bit value that is used to either send data to or get data from the device, includes the address of the device and the read/write bit. 
For instance:

If you want to read information from our device, the full 8 bit adress transfer is 11011001

If you want to write information to our device, the full 8 bit adress transfer is 11011000

So the real "address" is actually only the 7 bit value, but the full 8 bit value which is needed to send data back and forth contains the 7 bit address and the read/write bit. This is easy to see when the address is written out in binary. However, when it is converted into hex, if you convert just the 7bit value you get a different answer than if you convert the 7bit value and include also the read/write bit. (sometimes, manufacturers will say that you have two different addresses for each part- one for reading data and one for writing data! )

For the TAS5760, here is how this would look:

If you represent just the 7 bit address value in hex, it looks like this:

  7 Bit 
Binary Value
7 Bit Hex
Representation
SPK_SLEEP/ADR = "HIGH" 1101100 6C

If you represent the full 8 bit value needed to move data back and forth, it looks like this:

 

7 Bit 
Binary Value + Read/Write

Hex Representation
if R/W Bit is included

With Read/Write bit = "HIGH" 11011000 D8


In the industry, this has caused a little bit of confusion since different companies represent it differently. For the documentation for the TAS5760xx family of devices, we chose to not use hex, but instead give the full binary breakdown of the 8 bit value needed to transfer data back and forth. You see this in the latest data sheet. Unfortunately some earlier versions had the hex representations and some of the GUI tools still do (I think).

TAS5760 I2C address issue (8 bit)

Q:

For TAS5760, the I2C address is correct or not. Our FAE think the correct address should be  DA / D8  instead of 0x6C or 0x6D.

A:

The full 8 bit value that is used to either send data to or get data from the device, includes the address of the device and the read/write bit. 


For instance:

If you want to read information from our device, the full 8 bit adress transfer is 11011001

If you want to write information to our device, the full 8 bit adress transfer is 11011000

So the real "address" is actually only the 7 bit value, but the full 8 bit value which is needed to send data back and forth contains the 7 bit address and the read/write bit. This is easy to see when the address is written out in binary. However, when it is converted into hex, if you convert just the 7bit value you get a different answer than if you convert the 7bit value and include also the read/write bit. (sometimes, manufacturers will say that you have two different addresses for each part- one for reading data and one for writing data)

For the TAS5760, here is how this would look (and why the FAE thought).

If you represent just the 7 bit address value in hex, it looks like this:

  7 Bit 
Binary Value
7 Bit Hex
Representation
SPK_SLEEP/ADR = "HIGH" 1101100 6C

If you represent the full 8 bit value needed to move data back and forth, it looks like this:

 

7 Bit 
Binary Value + Read/Write

Hex Representation
if R/W Bit is included

With Read/Write bit = "HIGH" 11011000 D8

TAS5760: Maximum Junction Temperature

Original Question: Maximum Junction Temperature

Hello, can anyone tell me what the maximum junction temperature is for the TAS5760MDAPR General Purpose I2S Input Class D Amplifier? The data sheet lists the maximum ambient operating temperature (Ta), but it does not contain the maximum junction temperature. Thanks!

Verified Answer: RE: Maximum Junction Temperature by Don Dapkus

Hi,

It is 150C. 

TAS57xx Data Sheets Power Plot on page 1

Question: What does the graph of output power versus supply voltage on page one of the data sheets mean? Why are these numbers different than the tabular data?

Answer:

The solid line on the plot shows instantaneous power at 10% THD+N (i.e. well into clipping). The table shows instantaneous power at 0.1% distortion (i.e. right before clipping). For both of these, instantaneous power refers to the power which can be made for a short period of time. "Short period of time" just means "a period of time in which the heat dissipation in the device is not a factor." This is important because music is very dynamic, and short bursts of audio are much more prevalent than is a continuous signal like a sine wave.

The power of the solid curved line is higher because, as the amplifier is driven into clipping, the signal becomes more like a square wave than a sine wave, which has more power content. Therefore, a plot which contains 10% THD+N values will have higher numbers than a table which contains an unclipped signal.

So, both of those values shown are instantaneous, but one is just the power you get if you drive the signal further into clipping.

The dashed line from the plot on the front page shows how the thermal limitations of the system affect the power output. At some point, the continuous power diverges from the instantaneous power due to the heating which occurs in the device at higher power output levels. This dashed line is what occurs on our 2 layer EVM. In a customer system, it should look similar to this if they're using a 2 layer board of similar layout. If they are using a 4 layer board the dashed line will occur at a higher power level.

TAS57XX I2C port impedance during Power Down

Q: TAS5709 I2C port impedance during Power Down

What is the TAS5709 I2C port impedance when not enabled?


A: Re: TAS5709 I2C port impedance during Power Down

Powering down the device does not change in the I2C input, which implies that the I2C port impedance is Hi-Z. You should have no problem controlling two TAS5709's with one I2C bus.

TAS57xx SSTIMER Capacitor in BD Mode

The SSTIMER capacitor function is to give a softer transition after exiting shutdown mode. 

This soft start is required when the device is configured in AD mode to avoid POP and click issues. When in BD mode, there should be <<10mV of offset between PWM+ and PWM-, so this modulation does not require a soft transition ramp to start-up. 

Having SSTIMER capacitor in BD mode does not represent any problem, in fact will help avoiding pop noise. The SSTIMER capacitor size determines the start-up ramp, 2200pF is the maximum recommended value.

TAS57xx, drive headphones

Q: TAS57xx, drive headphones

Is it possible to use the OutA, OutB, OutC and OutD outputs of the TAS5705 / TAS5706 / TAS5716 (after some passive filtering) to directly drive headphones, with true ground? Is it possible to drive 4 such headphones with a single part? We would like the parts ount to a minimum and so a Digital, Quad amp is preferred. Please share some related application notes.

A: Re: TAS57xx, drive headphones

The TAS5706B and TAS5716 support 4 channel single ended configurations. A large DC blocking capacitor is required for a single ended load (see app notehttp://www.ti.com/litv/pdf/sloa119a for Class D filtering). Page 4 of the TAS5716 datasheet shows the amplifier configured in 4-channel single ended mode and Figures 24-28 on page 21 show the characterization for a single-ended 4 ohm load.

Thermal between TAS5711 and TAS5707.

Q: Thermal between TAS5711 and TAS5707.

Both TAS5711 and TAS5707 RDS(ON)=180mohms, why thermal gap ~ 12~15 degree C under the same test condition? Thanks, Ian.


A: Re: Thermal between TAS5711 and TAS5707.

The TAS5711 and TAS5707 should have the same thermal performance. However, the TAS5711EVM is considerably larger than the TAS5707EVM and therefore can keep the amplifier cooler during high power operation.

Using TAS570x in PBTL

Q: Using TAS570x in PBTL 

Almost all TAS570x must be paralleled after the LC filters.
Only TAS5711 and later amplifiers can be paralleled before the LC filters (i.e. right at the OUT pins).

What is the difference between TAS5706A and TAS5706B?

Q: What is the difference between TAS5706A and TAS5706B? 

 

TAS5706A and TAS5706B Differences
 
•           Stereo BTL support
•           2.1 support with external Power Stage
•           Stereo BTL support
•           2.1 support with external Power Stage
•           2.1 SE support (2x SE + 1x BTL)
•           4.0 SE support (4x SE)
•           Longer turn on/turn off time in SE mode (~ 700ms vs ~ 30ms)
•           Initially the TAS5706A also supported SE mode, but the power loss pop was an issue for some customers.
•           Some register values are different vs. TAS5706A
•           Slightly different power stage architecture vs. TAS5706A

What is the difference between TAS5731 and TAS5731M?

The attached .pdf shows the technical differences between the older TAS5731 and the newer TAS5731M. The TAS5731M has improvements to make it more robust in applications, so we recommend it be used in all new designs.

/cfs-file/__key/communityserver-discussions-components-files/6/6724.New-TAS5731M-vs-Old-TAS5731.pdf

 

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