TLV320DAC3203: I2S signal bypass to HPL/HPR output

Jesse Lee

Expert 1985 points

Part Number: TLV320DAC3203

hello

I want to tune the Audio EQ in the BT SOC.

I don't need digital-input aduio processing, and want the Audio signal routed from the I2S input pin to DAC, and then to the output amplifier.

Is there and setting method of this function? or the demo code ?

Thanks a lot!

over 5 years ago

0 Ivan Salazar over 5 years ago

TI__Guru* 95225 points

Hi Jesse,

A basic configuration of the device is available in the Application Reference Guide: www.ti.com/.../slau434.pdf example section 4.2 on page 75.
You would only need to adjust this to your system I2S clock settings and desired sampling frequency.
The features of the device are disabled by default, so if you do not enable them you would have the most basic operation of the device.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

0 Jesse Lee over 5 years ago in reply to Ivan Salazar

Expert 1985 points

V1.pdfHello

And we use TLV320DAC3203, find that it has no output.

The voltage level on REF (pin 17) is 0V.

could you help to provide some comments on fixing it??

Thanks

circuit link is

set The register configure as below:

const cfg_reg Tlv320dacData1[] = {

#----------- Power-up

#----------- Initialize to page 0

{ 0x00, 0x00},

#----------- Initialize the device through software reset

{ 0x01, 0x01 },

#----------- Power up the NDAC divider with value 1

{ 0x0b, 0x81 },

#----------- Power up the MDAC divider with value 4

#----------- For class-D mode, MDAC = I*4

{ 0x0c, 0x84 },

#----------- Program the OSR of DAC to 64

{ 0x0d, 0x00 },

{ 0x0e, 0x40 },

#----------- Set the DAC Mode to PRB_P8v

{ 0x3c, 0x08 },

#----------- Select page 1

{ 0x00 , 0x01 },

#----------- Disable internal crude AVdd in presence of external AVdd supply

#----------- or before powering up internal AVdd LDO

{ 0x01 , 0x08 },

#----------- Enable master analog power control

{ 0x02 , 0x00 },

#----------- Set the REF charging time to 40ms

{ 0x7b , 0x01 },

#----------- Set the input common mode to 0.9V and output common mode for headphone

#----------- to input common mode

{ 0x0a , 0x03 },

#----------- Set the DAC PTM mode to PTM_P1

{ 0x03 , 0x08 },

#----------- Set the DAC PTM mode to PTM_P1

{ 0x04 , 0x08 },

#----------- Route left DAC to HPL

{ 0x0c , 0x08 },

#----------- Route right DAC to HPR

{ 0x0d , 0x08 },

#----------- Unmute HPL driver

{ 0x10 , 0x00 },

#----------- Unmute HPR driver

{ 0x11 , 0x00 },

#----------- HP soft stepping settings for optimal pop performance at power up

#----------- Rpop used is 6k with N = 6 & soft step = 20usec.

{ 0x14 , 0x29 },

#----------- Power up HPL and HPR drivers

{ 0x09 , 0x30 },

#----------- Wait for 2.5 sec for soft stepping to take effect

#----------- Else read Page 1, Register 63d, D(7:6). When = “11” soft-stepping is complete

#----------- Switch to page 0

{ 0x00 , 0x00 },

#----------- Power up the left and right DAC channels and route the left channel I2S data

#----------- to left channel DAC and right channel I2S data to right channel DAC

{ 0x3f , 0xd4 },

#----------- Unmute the DAC digital volume control

{ 0x40 , 0x00 },

};

0 Jesse Lee over 5 years ago in reply to Jesse Lee

Expert 1985 points

6786.V1.pdfpost circuit again

0 Ivan Salazar over 5 years ago in reply to Jesse Lee

TI__Guru* 95225 points

Hi Jesse,

Do you want to use Class-D mode for the outputs or not?
From the clock settings I would think you want to use it, since MDAC = I*4, but then you don't configure registers 0x03 and 0x04 from page 1, so Class-D mode is not enabled.

Can you verify the I2C communication? You could try to read back the registers you've written. Not getting any voltage from VREF is not a good thing.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

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TLV320DAC3203: I2S signal bypass to HPL/HPR output