TLV320AIC3254: miniDSP GDE Process Flow and Config - ADC Output simply zeros

Miguel Carvalho

Part Number: TLV320AIC3254

Hi there,

We are testing a 192kHz sample rate through the miniDSP. We trying to configure the use of FIlter B which will introduce a -24dB gain error which will supposedly be fixed by a +4 shift (more info further). The AIC3254 is on a product in which I have i2c communication (via) DSP Driver and a McASP interface between the AIC3254 and the DSP. We thus interpret pps driver files register settings and configure the codec without a EVM board via i2c.

Attempting to replicate something similar to this post

AS SOON AS I CONFIGURE THE USE OF THE miniDSP_A the ADC samples are all zero.

I have been trying to configure the miniDSP for a simple process flow as below:

The Framework used is not the default 192kHz framwork as I would like to use Filter B for the bandwidth, the framwork used I assume uses filter B.

The process flow is setup as below:

With the SystemSettings code edited as follows:

(I am commenting out all the DAC settings as for now I only want to get the ADC running through the miniDSP, Is this fine?)

(I have also commented out any initialization, power up, routing and clock setup as this is done in the miniDSP driver, I will provide details further)

;-----------------------------------------------------------------------------------
; Software Reset
;-----------------------------------------------------------------------------------
	;reg[  0][  1] = 0x01	; Initialize the device through software reset
    ;reg[254][  0] = 0x0a	; Delay 10ms

;-----------------------------------------------------------------------------------
; Configure Power Supplies
;-----------------------------------------------------------------------------------
	%%if (%%prop(TargetBoard) == 2)
; AIC3254EVM-U specific configuration

	;reg[  1][  2] = 0xa9	; Power up AVDD LDO
	;reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection
	;reg[  1][  2] = 0xa1	; Enable Master Analog Power Control, AVDD LDO Powered
        
	%%else
; AIC3254EVM-K specific configuration        
	;reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection
	;reg[  1][  2] = 0x00	; Enable Master Analog Power Control
        
	%%endif
        
	;reg[  1][ 71] = 0x32	; Set the input power-up time to 3.1ms   
	;reg[  1][123] = 0x01	; Set REF charging time to 40ms (automatic)
;	;reg[254][  0] = 0x28	; Delay 40ms for REF to Power Up

;-----------------------------------------------------------------------------------
; Load miniDSP Code
;-----------------------------------------------------------------------------------
	PROGRAM_ADC		; miniDSP_A coefficients and instructions           
	;PROGRAM_DAC		; miniDSP_D coefficients and instructions

;-----------------------------------------------------------------------------------
; Signal Processing Settings
;-----------------------------------------------------------------------------------
	;reg[  0][ 60] = 0x00	; Use miniDSP_D for signal processing
	reg[  0][ 61] = 0x00	; Use miniDSP_A for signal processing

	%%if ("%%prop(FrameworkType)" == "AIC3254App8x4x")    
	reg[  0][ 17] = 0x08	; 8x Interpolation
	reg[  0][ 23] = 0x04	; 4x Decimation
	%%endif

	%%if ("%%prop(FrameworkType)" == "AIC3254App4x2x")    
	reg[  0][ 17] = 0x04	; 4x Interpolation
	reg[  0][ 23] = 0x02	; 2x Decimation
	%%endif

	%%if ("%%prop(FrameworkType)" == "AIC3254App2x1x")    
	reg[  0][ 17] = 0x02	; 2x Interpolation
	reg[  0][ 23] = 0x01	; 1x Decimation
	%%endif

	;IDAC  = %%prop(miniDSP_D_Cycles)
	IADC  = %%prop(miniDSP_A_Cycles)

	%%if (%%prop(miniDSP_A_Adaptive) == 1)
	;reg[  8][  1] = 0x04	; adaptive mode for ADC
	%%endif

	%%if (%%prop(miniDSP_D_Adaptive) == 1)
	;reg[ 44][  1] = 0x04	; adaptive mode for DAC
	%%endif

;-----------------------------------------------------------------------------------
; Clock and Interface Configuration
;-----------------------------------------------------------------------------------
; USB Audio supports 8kHz to 48kHz sample rates
; An external audio interface is required for 88.2kHz to 192kHz sample rates
;-----------------------------------------------------------------------------------
	%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)
	;reg[  0][  5] = 0x91	; P=1, R=1, J=8
	;reg[  0][  6] = 0x08	; P=1, R=1, J=8
	;reg[  0][  7] = 0x00	; D=0000 (MSB)
	;reg[  0][  8] = 0x00	; D=0000 (LSB)
	;reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	;reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	;reg[  0][ 13] = 0x00	; DOSR = 32 (MSB)
	;reg[  0][ 14] = 0x20	; DOSR = 32 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off 
	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on
	reg[  0][ 20] = 0x20	; AOSR = 32
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on

	%%endif

	%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)
	reg[  0][  5] = 0x91	; P=1, R=1, J=8
	reg[  0][  6] = 0x08	; P=1, R=1, J=8
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x00	; DOSR = 64 (MSB)
	reg[  0][ 14] = 0x40	; DOSR = 64 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on
	reg[  0][ 20] = 0x40	; AOSR = 64
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif

	%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)
	reg[  0][  5] = 0x91	; P=1, R=1, J=8
	reg[  0][  6] = 0x08	; P=1, R=1, J=8
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x00	; DOSR = 128 (MSB)
	reg[  0][ 14] = 0x80	; DOSR = 128 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on
	reg[  0][ 20] = 0x80	; AOSR = 128
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif

	%%if (%%prop(SampleRate) == 32000)
	reg[  0][  5] = 0x91	; P=1, R=1, J=8
	reg[  0][  6] = 0x08	; P=1, R=1, J=8
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x00	; DOSR = 192 (MSB)
	reg[  0][ 14] = 0xc0	; DOSR = 192 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0x8c	; MADC = 12, divider powered on
	reg[  0][ 20] = 0x80	; AOSR = 128
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif

	%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)
	reg[  0][  5] = 0x91	; P=1, R=1, J=8
	reg[  0][  6] = 0x08	; P=1, R=1, J=8
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x01	; DOSR = 256 (MSB)
	reg[  0][ 14] = 0x00	; DOSR = 256 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0x90	; MADC = 16, divider powered on
	reg[  0][ 20] = 0x80	; AOSR = 128
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif

	%%if (%%prop(SampleRate) == 16000)
	reg[  0][  5] = 0x91	; P=1, R=1, J=24
	reg[  0][  6] = 0x18	; P=1, R=1, J=24
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x01	; DOSR = 384 (MSB)
	reg[  0][ 14] = 0x80	; DOSR = 384 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0x98	; MADC = 24, divider powered on
	reg[  0][ 20] = 0x80	; AOSR = 128
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif

	%%if (%%prop(SampleRate) == 11025)
	reg[  0][  5] = 0x91	; P=1, R=1, J=16
	reg[  0][  6] = 0x10	; P=1, R=1, J=16
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x02	; DOSR = 512 (MSB)
	reg[  0][ 14] = 0x00	; DOSR = 512 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0xa0	; MADC = 32, divider powered on
	reg[  0][ 20] = 0x80	; AOSR = 128
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif

	%%if (%%prop(SampleRate) == 8000)
	reg[  0][  5] = 0x91	; P=1, R=1, J=24
	reg[  0][  6] = 0x18	; P=1, R=1, J=24
	reg[  0][  7] = 0x00	; D=0000 (MSB)
	reg[  0][  8] = 0x00	; D=0000 (LSB)
	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
	reg[  0][ 13] = 0x03	; DOSR = 768 (MSB)
	reg[  0][ 14] = 0x00	; DOSR = 768 (LSB)
	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
	reg[  0][ 19] = 0xb0	; MADC = 48, divider powered on
	reg[  0][ 20] = 0x80	; AOSR = 128
	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
	%%endif



;-----------------------------------------------------------------------------------
; ADC Channel Configuration
;-----------------------------------------------------------------------------------
	;reg[  1][ 51] = 0x40	; Mic Bias enabled, Source = Avdd, 1.25V

	%%if (%%prop(TargetBoard) == 2)
; AIC3254EVM-U specific configuration
	;reg[  1][ 52] = 0x10	; Route IN2L to LEFT_P with 10K input impedance
	;reg[  1][ 54] = 0x40	; Route CM1L to LEFT_M with 10K input impedance
	;reg[  1][ 55] = 0x10	; Route IN2R to RIGHT_P with 10K input impedance

	%%else
; AIC3254EVM-K specific configuration
	;reg[  1][ 52] = 0x40	; Route IN1L to LEFT_P with 10K input impedance
	;reg[  1][ 54] = 0x40	; Route CM1L to LEFT_M with 10K input impedance
	;reg[  1][ 55] = 0x40	; Route IN1R to RIGHT_P with 10K input impedance

	%%endif
	
	;reg[  1][ 57] = 0x40	; Route CM1R to RIGHT_M with 10K input impedance
	;reg[  1][ 59] = 0x00	; Enable MicPGA_L Gain Control, 0dB
	;reg[  1][ 60] = 0x00	; Enable MicPGA_R Gain Control, 0dB
	;reg[  0][ 81] = 0xc0	; Power up LADC/RADC
	;reg[  0][ 82] = 0x00	; Unmute LADC/RADC

;-----------------------------------------------------------------------------------
; DAC Channel Configuration
;-----------------------------------------------------------------------------------
	;reg[  1][ 20] = 0x25	; De-pop: 5 time constants, 6k resistance
	;reg[  1][ 12] = 0x08	; Route LDAC to HPL
	;reg[  1][ 13] = 0x08	; Route RDAC to HPR
	;reg[  1][ 14] = 0x08	; Route LDAC to LOL
	;reg[  1][ 15] = 0x08	; Route LDAC to LOR
	;reg[  0][ 63] = 0xd4	; Power up LDAC/RDAC w/ soft stepping
	;reg[  1][ 16] = 0x00	; Unmute HPL driver, 0dB Gain
	;reg[  1][ 17] = 0x00	; Unmute HPR driver, 0dB Gain
	;reg[  1][ 18] = 0x00	; Unmute LOL driver, 0dB Gain
	;reg[  1][ 19] = 0x00	; Unmute LOR driver, 0dB Gain
	;reg[  1][  9] = 0x3c	; Power up HPL/HPR and LOL/LOR drivers
	;reg[  0][ 64] = 0x00	; Unmute LDAC/RDAC

As shown above the following are some highlighted configuration settings (are they correct)?

Clock Settings:

PLL is used = 98.304MHZ = CODEC_CLKIN

NADC = 2

MADC = 8

AOSR = 32

CODEC_CLKIN = NADC x MADC x ADC_FS = 2 x 4x 192000 = 98.304MHZ (Is this correct?)

I see in the clock distribution tree there is an indication that the mini DSP clock generation branches off after the NADC does this still mean my clock setup is correct, is it somewhat confusing to me?

Also in the reference post they use 2x decimation, Im not exactly sure why and where this 2x decimation comes from as I was under the impression the decimation is done with the hardware filters (Filter C) before the miniDSP based on the framework. How does it fit in with the clock rate settings and sample rate?

I have attached the process flow in case it is needed:

TC5 Test 2.zip

over 5 years ago

0 Diego Melendez over 5 years ago

TI__Guru 57800 points

Hi, Miguel,

As you commented some of the initialization registers for the codec, I wonder if there is a problem with the device configuration as typically the sequence followed in system settings code should be followed. Have you tried to run the application with the complete systems settings code?. The decimation filter when the miniDSP is used actually is determined by the Decimation block, which should match the framework selected.

I will take a look to your process flow and settings in detail, but it may take me some time to experiment on my end, so appreciate your patience in advance.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Miguel Carvalho over 5 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego,

Thank you for your reply.

I have not, although the CODEC is running perfectly until I "USE MINI DSP" so I am quite sure that the initialization and power up is correct and functioning?

Thank you for looking at the process flow I look forward to your response.

Kind regards
Miguel

0 Miguel Carvalho over 5 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego, any progress on getting the process flow up and running?

0 Miguel Carvalho over 5 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego,

I am still not able to get the audio through the miniDSP. Are you still trying to find time to look at the process flow in more detail?

0 Diego Melendez over 5 years ago in reply to Miguel Carvalho

TI__Guru 57800 points

Miguel,

Sorry for the delay, was swamped lately and missed this one. I loaded your process flow in the EVM and noticed that the System settings code is not commented in the .PFW file. I downloaded that code into the EVM and I can see the ADC output in DOUT. Then, I tried loading the system settings code you shared in this post after a HW reset on the device and the ADC output (DOUT) is lost. I noticed you are commenting not only the initialization registers, but also the ADC and PLL configuration registers, which is not right, After un-commenting those lines, I got DOUT signal back. Please refer to below System Settings code I used:

;-----------------------------------------------------------------------------------
; Software Reset
;-----------------------------------------------------------------------------------
reg[ 0][ 1] = 0x01 ; Initialize the device through software reset
reg[254][ 0] = 0x0a ; Delay 10ms

;-----------------------------------------------------------------------------------
; Configure Power Supplies
;-----------------------------------------------------------------------------------
%%if (%%prop(TargetBoard) == 2)
; AIC3254EVM-U specific configuration

;reg[ 1][ 2] = 0xa9 ; Power up AVDD LDO
;reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection
;reg[ 1][ 2] = 0xa1 ; Enable Master Analog Power Control, AVDD LDO Powered

%%else
; AIC3254EVM-K specific configuration 
reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection
reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control

%%endif

reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms 
reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic)
reg[254][ 0] = 0x28 ; Delay 40ms for REF to Power Up

;-----------------------------------------------------------------------------------
; Load miniDSP Code
;-----------------------------------------------------------------------------------
PROGRAM_ADC ; miniDSP_A coefficients and instructions 
;PROGRAM_DAC ; miniDSP_D coefficients and instructions

;-----------------------------------------------------------------------------------
; Signal Processing Settings
;-----------------------------------------------------------------------------------
;reg[ 0][ 60] = 0x00 ; Use miniDSP_D for signal processing
reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing

%%if ("%%prop(FrameworkType)" == "AIC3254App8x4x") 
reg[ 0][ 17] = 0x08 ; 8x Interpolation
reg[ 0][ 23] = 0x04 ; 4x Decimation
%%endif

%%if ("%%prop(FrameworkType)" == "AIC3254App4x2x") 
reg[ 0][ 17] = 0x04 ; 4x Interpolation
reg[ 0][ 23] = 0x02 ; 2x Decimation
%%endif

%%if ("%%prop(FrameworkType)" == "AIC3254App2x1x") 
reg[ 0][ 17] = 0x02 ; 2x Interpolation
reg[ 0][ 23] = 0x01 ; 1x Decimation
%%endif

;IDAC = %%prop(miniDSP_D_Cycles)
IADC = %%prop(miniDSP_A_Cycles)

%%if (%%prop(miniDSP_A_Adaptive) == 1)
reg[ 8][ 1] = 0x04 ; adaptive mode for ADC
%%endif

%%if (%%prop(miniDSP_D_Adaptive) == 1)
;reg[ 44][ 1] = 0x04 ; adaptive mode for DAC
%%endif

;-----------------------------------------------------------------------------------
; Clock and Interface Configuration
;-----------------------------------------------------------------------------------
; USB Audio supports 8kHz to 48kHz sample rates
; An external audio interface is required for 88.2kHz to 192kHz sample rates
;-----------------------------------------------------------------------------------
%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB)
reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off 
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x20 ; AOSR = 32
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on

%%endif

%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB)
reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x40 ; AOSR = 64
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 32000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB)
reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 16000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 11025)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16
reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 8000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif



;-----------------------------------------------------------------------------------
; ADC Channel Configuration
;-----------------------------------------------------------------------------------
reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V

%%if (%%prop(TargetBoard) == 2)
; AIC3254EVM-U specific configuration
reg[ 1][ 52] = 0x10 ; Route IN2L to LEFT_P with 10K input impedance
reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
reg[ 1][ 55] = 0x10 ; Route IN2R to RIGHT_P with 10K input impedance

%%else
; AIC3254EVM-K specific configuration
reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance
reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance

%%endif

reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance
reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB
reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB
reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC
reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC

;-----------------------------------------------------------------------------------
; DAC Channel Configuration
;-----------------------------------------------------------------------------------
;reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance
;reg[ 1][ 12] = 0x08 ; Route LDAC to HPL
;reg[ 1][ 13] = 0x08 ; Route RDAC to HPR
;reg[ 1][ 14] = 0x08 ; Route LDAC to LOL
;reg[ 1][ 15] = 0x08 ; Route LDAC to LOR
;reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping
;reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain
;reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain
;reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain
;reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain
;reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers
;reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Miguel Carvalho over 5 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego

Thank you for your reply.

RE: " I noticed you are commenting not only the initialization registers, but also the ADC and PLL configuration registers, which is not right"

If you look in my initial question I detailed some of the ADC and PLL settings (which is why I comment out the process flow setup - I am not using the EVM).

Clock Settings:

PLL is used = 98.304MHZ = CODEC_CLKIN

NADC = 2

MADC = 8

AOSR = 32

CODEC_CLKIN = NADC x MADC x ADC_FS = 2 x 4x 192000 = 98.304MHZ (Is this correct?)
"

To provide a bigger picture the PLL is setup as follows:

The PLL Uses the MCLK at 14.7456MHz.

R = 1

P = 3

J.D = 20.0

This setup is currently being used without the miniDSP and is working correctly.

I have tried with NADC = 4 and MADC = 4 (setup w/o miniDSP) AND NADC = 2 and MADC = 8 to no success.

Looking at this tree I see that the miniDSP gets its clock after the NADC divider.

WHat exactly should the clock rate be for the miniDSP? Maybe my problem lies somewhere here?

Best Regards

Miguel

0 Diego Melendez over 5 years ago in reply to Miguel Carvalho

TI__Guru 57800 points

Hi, Miguel,

Thanks for the feedback. The PLL calculation is right, but for that, you need to enable it and load the proper values to the PLL coefficients. What are the values you are currently using?. Can you share the exact register writes you are sending to the PLL outside the system settings code provided?.

Also, please note that in the System Settings code you provided, the ADCs are not turned ON, which result in zero DOUT signal. Are you configuring the ADC outside of the System settings code?.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Miguel Carvalho over 5 years ago in reply to Diego Melendez

Prodigy 170 points

Hi Diego

Thank you for your response. Below please find the configuration below, I hope it is understandable:

FORMAT:

AIC3254_PAGE_X, 0xXX , 0xXX
PAGE_0 , Register Number(HEX) , Register Value(HEX)

// Setup the clock multiplexers:
// - Low PLL clock range
// - PLL input clock is MCLK
// - CODEC_CLKIN = PLL Clock

AIC3254_PAGE_0, 0x04, 0x03

// - Choose R = 1 and P = 3
// - Calculate J.D = 20.0 --> J = 20 and D = 0
// - This results in a PLL_CLK of 98.304 MHz

// Program PLL P and R values and power-up PLL
PAGE_0, 0x05, 0xB1

// Program PLL J value
AIC3254_PAGE_0, 0x06, 0x14

// Program PLL D value
AIC3254_PAGE_0, 0x07, 0x00 MSB
AIC3254_PAGE_0, 0x08, 0x00 LSB

// Configure the input channel (ADC)
// Setup NADC and power-up divider

// NADC = 4
AIC3254_PAGE_0, 0x12, 0x84

// Setup MADC and power-up divider
AIC3254_PAGE_0, 0x13, 0x84

// Setup AOSR = 32
AIC3254_PAGE_0, 0x14, 0x20

RE: The ADCs being turned ON

Yes the ADC is configured elsewhere. A confirmation of this is that if I simply switch the Register which Enables the use of the miniDSP to not use it, then the ADC samples as expected.

Here is the power up config:

AIC3254_PAGE_0, 0x51 , 0xC0

Thank you very much for your assistance in this regard.

Miguel

0 Diego Melendez over 5 years ago in reply to Miguel Carvalho

TI__Guru 57800 points

Miguel,

Thanks for the additional information. I looked at the register settings and seems that the PLL is correctly configured, I don't think the clocks could be the issue. One thing you need to take into account is that even if the clock settings are not correct or appropriate according to the number of required miniDSP cycles, you should see something at the ADC output, may be distorted data but something should be seen. I mention that because I think the issue lies somewhere else.

If you have an initialization sequence for the device, where the miniDSP is not used, and the device works, then if after loading the miniDSP code you get no output it suggests that when loading the miniDSP code, some registers are being overwritten, causing the device to not work anymore. In order to identify the possible register which could be causing the issues, I would like to know the complete register setting you use initialize the codec, and then what is the exact code loaded to your codec when enabling the use of the miniDSP. With this I could track what could be the issue and may be able to suggest a workaround. I must mention that in general, when the miniDSP is used, the exported code from PPS is used and is not dynamically changed to disable miniDSP.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

Audio

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TLV320AIC3254: miniDSP GDE Process Flow and Config - ADC Output simply zeros