TLV320AIC3107: TLV320AIC3107 DAC output noise problem

Hi Steve,

Thank you for your reply.  Did you missed the link to the application report?

please repost.....

Regards,

Stalker

Stalker,

Sorry about that. I've fixed the link above.

best regards
-Steve

Hi Steve,

 

 

Thank you for the application report it is very helpful. I did 4 measurements and here the results:

 

Test 1 I short the scope input to get base line of the equipment and I am getting roughly -55dB, Tek00001.PNG

 

Test 2 connect scope to the LOP output of the CODEC, CODEC is powered up and initialized I2S bus is still idling ;noise floor remains the same. TEK00002.PNG

 

Test 3 DSP is generating 1000HZ and noise floor raised up to -45dB Tek00003.png

 

Test4 disable I2S bus noise floor remains at -45 dB tek00004.pNG

 

Looking at the TLV320AIC3107 data sheet page 15 figure 9 where it shows noise floor around -120dB, definitely shows I am doing something wrong. I did try to add 10K pull down resistor (ie to much test set up ) but it didn’t really help, noise floor remains at the same -45dB level.

 Any word of advise?

Thank you,

 

 

Stalker

Stalker,

This is on the EVM or your own board?

The EVM has the LPF on the line outs by default.

Can you provide your full register configuration? also provide your MCLK frequency (if you are using an MCLK) and your desired FS,BCLK, data format, etc...

One thing that would really increase the noise is if you set the gain on the output blocks to +9dB.

Hi Steve,


Thank you for your reply.


This is my own hardware;
master clock 16 MHZ provided externally
sampling frequency 48KHZ
I2S bus

also you mentioned about "+9dB gain" I did see this magic number through data sheet, but I am not sure which register is this.
Is it register 43, 44 DAC gain control? according to the data sheet gain settings for those 0dB to -63.5dB;
I am using 0 dB settings;

Can you please double check and advise

Regards,

Stalker

Stalker,

The +9dB would be for the Right and Left LOP outputs, Register 93 and 86.

Did you mean to attach the register configuration to your last message? I didn't see anything

I will need the full register configuration.

best regards,
-Steve wilson

Hi Steve,


Please see below, entire init sequence also registers 93/86 set to 0dB gain:

Regards,

Stalker


temp = 0; //select page 0
result = i2cWrite(AIC3101_I2C_ADDR, AIC3101_PAGE_SELECT_REG, &temp, 1);

temp = 0x00; // Set ADC/DAC sampling rate equal F sampling ie no dividers
result = result & i2cWriteBlocking(AIC3101_I2C_ADDR, AIC3101_SAMPLE_RATE_REG, &temp, 1);

// Sampling frequency should be equal WCLK, BCLK = 16 bit * 2(L/R) * Fsampling

temp = 0x02; //set PLL and CLKDIV input to MCLK pin; pll N = 2
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_CLK_GEN_REG, &temp, 1);


// PLL Bellow, also with PLL I can get min sampling frequency around 39KHZ
// also it setting up sampling rate 48kHZ based on 16MHZ MCLK
// F ADC ( or DAC) = (MCK * K * R) / (2048 * P), where K is J.D

temp = 0x0; //set CODEC clock source to PLL
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_CLK_REG, &temp, 1);

temp = 0x81; // enable PLL, PLL P = 1, Q = 0
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_PLL_A_REG, &temp, 1);

temp = 0x18; // PLL J = 6; PLL k = J.D
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_PLL_B_REG, &temp, 1);

temp = 0x16; // PLL D =1440 = 5A0 = 101 1010 0000 => 0001 0110 10 0000 =>
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_PLL_C_REG, &temp, 1);

temp = 0x80; // D =1440 rest of the number from above
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_PLL_D_REG, &temp, 1);

temp = 0x01; // PLL R = 1
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_OVERF_REG, &temp, 1);
//----------- END PLL


temp = 0xD0; //set BCLK as an output ; WCLK as an output
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_ASDI_A_REG, &temp, 1);

temp = 0x0; // Set I2S mode; 16 bit data width
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_ASDI_B_REG, &temp, 1);

temp = 0x0A; //AGC Fsref = 48 khzLeft DAC plays left channel data and Right channel play right data
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_DATA_PATH_REG, &temp, 1);

temp = 0; //Make sure all bypass switches are off ie normal operation
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_ANALOG_BYPASS_REG, &temp, 1);

temp = 0x0; //Set output common voltage 1.35V according table 5 in data sheet
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_HPWR_OUT_CNTR_REG, &temp, 1);

//---------------- Setting Input level MIC2L/R ADC L

temp = 0x0F; // Set MIC2L to left ADC 0dB Attenuation; MIC2R is not connected to the left ADC
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_MIC2L_TO_LADC_REG, &temp, 1);

temp = 0x7F; // Enable left ADC power; Disable MIC1_LP
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_MIC1LP_CNTR_REG, &temp, 1);

//---------- Setting Input Level MIC2L/R ADC R

temp = 0xF0; // Set MIC2R to right ADC 0dB Attenuation; MIC2L is not connected to the right ADC
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_MIC2R_TO_RADC_REG, &temp, 1);

temp = 0x7F; // Enable right ADC power; Disable MIC1_RP
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_MIC1RP_CNTR_REG, &temp, 1);

temp = 0;
result =result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_LEFT_AGC_CNTR_REG_A, &temp, 1);
result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_RIGHT_AGC_CNTR_REG_A, &temp, 1);

temp = value;
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_LADC_PGA_REG, &temp, 1);
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_RADC_PGA_REG, &temp, 1);

//-------------- Now, enable DAC and LOP drivers , also DAC doesnt have gains only attenuations

uint8_t temp = 0x0; // Unmute left DAC and set Gain 0dB
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_LDAC_VOLUME_REG, &temp, 1);

temp = 0xE0; // Enable Left DAC; Enable Right DAC; HPLCOM independed single ended output
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_DAC_PWR_CNTR_REG, &temp, 1);

temp = 0x50; // Select Left DAC L3 path to left LOP and DAC R3 path to right LOP;
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_DAC_OUT_SW_REG, &temp, 1);

temp = 0x09; //unmute right LOP Set gain 1dB
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_RIGHT_LOP_OUT_CNTR, &temp, 1);

temp = 0x09; //unmute left LOP Set gain 1dB
result = result & i2cWrite(AIC3101_I2C_ADDR, AIC3101_LEFT_LOP_OUT_CNTR, &temp, 1);

Steve,

Did you have a chance to look at this?

please advise...

Hi Steve,

Any updates?

Hi Steve,

Can you have look below, please?

Stalker,

If this is only happening when you are communicating with the MCU, and not when you loop the ADC to the DAC, then this is most likely an interface problem.

can you post your register configuration along with your MCLK frequency, your desired Fs, and audio format?

best regards,
-STeve Wilson

Hi Steve,

Thank you for your reply.

MCLK = 16 MHZ; Fs = 48KHZ;
all we do we: we generating sine wave with MCU and sending over I2S

register configuration already posted , please see above

Stalker,

Can you capture a screen shot of the I2S signals? I'd like to see DATA, BCLK and FSYNC (WCLK) all on the same window.

-Steve

Hi Steve,

Thank you for your reply. See Attached...

Yellow BCLK

Blue WCLK

Magenta CODEC Data IN ie data what is feeding in to the CODEC

Regards,

Stalker

Stalker,

Is the MAgenta codec Data IN line Showing audio data? or is that with no audio playing?

The Image doesn't tell us a lot since the AIC3107 is in master mode and IT is generating the BCLK and WCLK. What I really want to be sure of is that your processor is configured properly. what processor are you using, and do you have the configuration for the audio bus?

best regards
-STeve Wilson

Hi Steve,

Thank you for your reply. we are using Nordic NRF52832 . Bellow is CPU configuration for I2S:

Regards,

Stalker

uint32_t err_code;
nrf_drv_i2s_config_t config = NRF_DRV_I2S_DEFAULT_CONFIG;

config.mck_pin = codecMckPin;
config.sck_pin = codecSckPin;
config.lrck_pin = codecLrckPin;
config.sdout_pin = codecsDoutPin;
config.sdin_pin = codecsDinPin;

config.mode = NRF_I2S_MODE_SLAVE; 
config.format = NRF_I2S_FORMAT_I2S;
config.sample_width = NRF_I2S_SWIDTH_16BIT;
config.mck_setup = NRF_I2S_MCK_32MDIV2; // MCLK 16MHZ
config.channels = NRF_I2S_CHANNELS_STEREO;
err_code = nrf_drv_i2s_init(&config, data_handler);

Stalker,

and was the screenshot taken when the processor was providing data?

best regards,
-Steve wilson

Stalker,

I was convinced this was a minor formatting issue, but I don't see anything. Can you send me the Sine wave file you are using?

-Steve Wilson

Hi Steve,

Thank you for your reply. I am not playing sinewave file I am generating 256 samples in I2S ISR and placing them in the buffer which is transferring over I2S to DAC .

uint32_t * p_word = outputBuffer;  // pointer to DAC output buffer

float a;
int16_t b = 0;

static uint16_t outputSigIndex = 0;

for (int i = 0; i < I2S_BUFFER_SIZE; i++){

a = (((float)testSignalFreq) * 2.f * PI * outputSigIndex ) / testSignalSampleFreq;
b = (int16_t)(testSignalAmplitude * (arm_sin_f32 (a))); 
((uint16_t *)p_word)[0] = b; // Left Channel
((uint16_t *)p_word)[1] = b; // Right Channel 
p_word++; 

if (a >= 2.f * PI){ // full wave cycle 
outputSigIndex = 1; 
}else{
outputSigIndex = outputSigIndex + 1; 
}

}

 

Regards,

Stalker

Stalker,  

Can you get a sound sample and scope shot of the analog output when the tone is playing, and after it is done and the noise floor is still higher?

best regards,

-Steve Wilson

Hi Steve.

please see below. also do you want me to record actual audio file as well, ie *.wav? Please advise 

Regards,

Stalker.

When generating tone:

 

Tone stop

Reset and re-init CODEC

Steve,

Any updates. Please advise.

Regards,

Stalker

Hi Steve,

Any updates?

Stalker,

I will set up an EVM with your configuration in the lab and send back measurements. I won't be at the office monday so Tuesday is more likely.

best regards,
-Steve Wilson

Thank you Sir, looking forward to your reply

Hi Steve,

Any updates?

Please advise

Hi Steve,

Any updates?

Hi Steve,

Any updates?

Stalker,

Having tested the EVM in the Lab with your settings, I can't explain why you are getting such a high noise floor. For me the noise floor sits at about -110dbr over the audio band.

I did have some issues initially where I was seeing exactly what you were, but it was related to the settings on the USBMODEVM. essentially the if I had the "external mclk" switch on while providing the mclk at the PSIA input, it was getting some sort of reflection which caused some glitching. once I turned the external mclk switch off, the problem resolved.

Your MCLK is coming from your processor, correct? do you have a schematic you can share?

best regards,
-Steve Wilson