Part Number: TLV320AIC24K
With regards to the TLV320AIC24KIPFBG4 we have two questions with regards to the I2C interface.
On the datasheet the Rise time (tr) of both SDA and SCL signals is specified as 300ns max. Since we are only operating at a SCL clock frequency of 100KHz can the limit be increased to 1000ns? Note that the reason I am suggesting 1000ns is because many other I2C devices allow this for slower clock frequencies – for example see datasheet for TCA9539RTWR and TCA9555RTWR.
Is there spike / glitch filtering / suppression on the SCL & SDA I2C inputs? Note that it has been observed that many other ICs have 50ns spike suppression on these inputs and the parameter is normally called “tsp”. Even the TLV320AIC23B (similar device from same family) has it. In addition, the TCA9539RTWR and TCA9555RTWR also have the spike suppression.
Look forward to you your reply.
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In reply to Steve-Wilson:
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