TLV320AIC3106: Need MCLK and I2C Signal Integration Specifications for TLV320AIC3106

Wayne Chen (ex FAE)

Part Number: TLV320AIC3106

Hi Sirs,

One question from my customers. Would you please advise the AIC3106's signal integrity specification of MCLK and I2C as we specified for I2S BCLK, LRCK and DATA on the AIC3106 datasheet?

Thank you and Best regards,

Wayne Chen
11/26/2018

over 5 years ago

0 Steve-Wilson over 5 years ago

TI__Mastermind 30030 points

Hello Wayne,

What exactly is your customer looking for? The MCLK is not part of the I2S standard, which is why it was not included in the diagrams.

There are some restrictions on the MCLK for certain configurations. you can find more information in This application report.

Best regards,

-Steve Wilson

0 Wayne Chen (ex FAE) over 5 years ago in reply to Steve-Wilson

Guru 15950 points

Thanks for your concern, Steve. The MCLK and I2C are not a part of the I2S, however, my customer needs to know SI specifications for AIC3106 so they can follow it up to design and test circuitries to ensure AIC3106’s operation.

Wayne Chen
11/27/2018

0 Steve-Wilson over 5 years ago in reply to Wayne Chen (ex FAE)

TI__Mastermind 30030 points

Wayne,

I2C communications timing is on page 44 of the data sheet.

Mclk can be 512 kHz to 50 MHz (also in data sheet) Should be a square wave.

best regards,
-Steve Wilson

0 Wayne Chen (ex FAE) over 5 years ago in reply to Steve-Wilson

Guru 15950 points

Thanks a lot Steve. However, it is not possible for customer to send perfect square waves thus we need rise time, fall time, setup time and hold time specifications for system certifications.

Thanks a lot,

Wayne Chen
11/28/2019

0 Steve-Wilson over 5 years ago in reply to Wayne Chen (ex FAE)

TI__Mastermind 30030 points

Wayne,

What is the desired MCLK frequency?

-Steve Wilson

0 Wayne Chen (ex FAE) over 5 years ago in reply to Steve-Wilson

Guru 15950 points

Hi Wilson,

Please provide MCLK's signal integrity suggestion based on customer's 12.288MHz design.

Thank you and Best regards,

Wayne Chen
12/07/2018

0 Steve-Wilson over 5 years ago in reply to Wayne Chen (ex FAE)

TI__Mastermind 30030 points

Wayne,
the Mclk signal integrity would be evaluated at the MCLK MAX, not 12.288 Mhz, the MCLK MAX is 50MHz, so you can imagine the relevance of the rise/fall and Setup/hold for 12.288Mhz,

at 50Mhz, the entire period of the MCLK is 20nSec. So the rise/fall times would need to be pretty quick, lets assume that the rise/fall max is in the 3-4 nsec range with setup/hold MIN in the 5-6 nsec range. ie 4+4+6+6= 20nsec

For an MCLK of 12.288 nsec. The rise/fall limitations relax since the entire period is 80nsec. do you anticipate their rise/fall being greater than 20-30 nsec?

best regards,
-Steve wilson

0 Wayne Chen (ex FAE) over 5 years ago in reply to Steve-Wilson

Guru 15950 points

Thank you for your advise, Steve...Wayne Chen

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TLV320AIC3106: Need MCLK and I2C Signal Integration Specifications for TLV320AIC3106