PCM1808: The I2S DOUT signal is mostly high on LRCLK transitions

gary grutzek

Part Number: PCM1808

Hi There,

I'm feeding the PCM1808 ADC in master mode with an LRCLK, BCLK and a MCLK. Watching the DOUT signal one can see that it is mostly high on LRCLK transitions (regardless of the analog input). Any Idea why this is happening? I've checked the VREF pin, tested several devices, used another clock circuit at different sampling rates.

Thanks,

Gary

over 5 years ago

0 Steve-Wilson over 5 years ago

TI__Mastermind 30030 points

Gary,

I'm not particularly familiar with the Rigol scopes, but this doesn't look like a single trigger, can you confirm?

best regards,
-Steve wilson

0 gary grutzek over 5 years ago in reply to Steve-Wilson

Prodigy 50 points

Sorry Steve, was just a bad picture. It's hopefully more clearly now.

The blue line is the LRCLK at 8kHz.
32 Bits per channel.
MCLK is 256*fs.
FMT, MD0, MD1 are kept low
Also tried many other configurations

Best,

Gary

0 gary grutzek over 5 years ago in reply to gary grutzek

Prodigy 50 points

0 gary grutzek over 5 years ago in reply to gary grutzek

Prodigy 50 points

No idea anyone?

0 Steve-Wilson over 5 years ago in reply to gary grutzek

TI__Mastermind 30030 points

Hi Gary,

Im looping in another engineer that supports this device, do you have a schematic by chance?

best regards,
-Steve wilson

0 gary grutzek over 5 years ago in reply to Steve-Wilson

Prodigy 50 points

Hi Steve,

thanks, sorry no schematic at hand. It's a basic test circuit with an input filter and all caps as specified in the datasheet. It is air-wired to an ESP32 microcontroller which is generating all the clocks.

Best,

Gary

0 Andy Peters over 5 years ago in reply to gary grutzek

Genius 3945 points

Looks like maybe your reference isn't bypassed properly or is shorted or something. Also make sure that all of the other power supply pins are properly bypassed.

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PCM1808: The I2S DOUT signal is mostly high on LRCLK transitions